These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / soc / tegra / fuse / tegra-apbmisc.c

diff --git a/kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c b/kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c
index 3bf5aba..5b18f6f 100644 (file)
--- a/kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -21,15 +21,21 @@
 #include <linux/io.h>
 
 #include <soc/tegra/fuse.h>
+#include <soc/tegra/common.h>
 
 #include "fuse.h"
 
-#define APBMISC_BASE   0x70000800
-#define APBMISC_SIZE   0x64
 #define FUSE_SKU_INFO  0x10
 
+#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT     4
+#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
+       (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
+#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT        \
+       (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
+
 static void __iomem *apbmisc_base;
 static void __iomem *strapping_base;
+static bool long_ram_code;
 
 u32 tegra_read_chipid(void)
 {
@@ -54,6 +60,18 @@ u32 tegra_read_straps(void)
                return 0;
 }
 
+u32 tegra_read_ram_code(void)
+{
+       u32 straps = tegra_read_straps();
+
+       if (long_ram_code)
+               straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
+       else
+               straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
+
+       return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
+}
+
 static const struct of_device_id apbmisc_match[] __initconst = {
        { .compatible = "nvidia,tegra20-apbmisc", },
        {},
@@ -76,8 +94,8 @@ void __init tegra_init_revision(void)
                rev = TEGRA_REVISION_A02;
                break;
        case 3:
-               if (chip_id == TEGRA20 && (tegra20_spare_fuse_early(18) ||
-                                          tegra20_spare_fuse_early(19)))
+               if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
+                                          tegra_fuse_read_spare(19)))
                        rev = TEGRA_REVISION_A03p;
                else
                        rev = TEGRA_REVISION_A03;
@@ -91,25 +109,74 @@ void __init tegra_init_revision(void)
 
        tegra_sku_info.revision = rev;
 
-       if (chip_id == TEGRA20)
-               tegra_sku_info.sku_id = tegra20_fuse_early(FUSE_SKU_INFO);
-       else
-               tegra_sku_info.sku_id = tegra30_fuse_readl(FUSE_SKU_INFO);
+       tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
 }
 
 void __init tegra_init_apbmisc(void)
 {
+       struct resource apbmisc, straps;
        struct device_node *np;
 
        np = of_find_matching_node(NULL, apbmisc_match);
-       apbmisc_base = of_iomap(np, 0);
-       if (!apbmisc_base) {
-               pr_warn("ioremap tegra apbmisc failed. using %08x instead\n",
-                       APBMISC_BASE);
-               apbmisc_base = ioremap(APBMISC_BASE, APBMISC_SIZE);
+       if (!np) {
+               /*
+                * Fall back to legacy initialization for 32-bit ARM only. All
+                * 64-bit ARM device tree files for Tegra are required to have
+                * an APBMISC node.
+                *
+                * This is for backwards-compatibility with old device trees
+                * that didn't contain an APBMISC node.
+                */
+               if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
+                       /* APBMISC registers (chip revision, ...) */
+                       apbmisc.start = 0x70000800;
+                       apbmisc.end = 0x70000863;
+                       apbmisc.flags = IORESOURCE_MEM;
+
+                       /* strapping options */
+                       if (tegra_get_chip_id() == TEGRA124) {
+                               straps.start = 0x7000e864;
+                               straps.end = 0x7000e867;
+                       } else {
+                               straps.start = 0x70000008;
+                               straps.end = 0x7000000b;
+                       }
+
+                       straps.flags = IORESOURCE_MEM;
+
+                       pr_warn("Using APBMISC region %pR\n", &apbmisc);
+                       pr_warn("Using strapping options registers %pR\n",
+                               &straps);
+               } else {
+                       /*
+                        * At this point we're not running on Tegra, so play
+                        * nice with multi-platform kernels.
+                        */
+                       return;
+               }
+       } else {
+               /*
+                * Extract information from the device tree if we've found a
+                * matching node.
+                */
+               if (of_address_to_resource(np, 0, &apbmisc) < 0) {
+                       pr_err("failed to get APBMISC registers\n");
+                       return;
+               }
+
+               if (of_address_to_resource(np, 1, &straps) < 0) {
+                       pr_err("failed to get strapping options registers\n");
+                       return;
+               }
        }
 
-       strapping_base = of_iomap(np, 1);
+       apbmisc_base = ioremap_nocache(apbmisc.start, resource_size(&apbmisc));
+       if (!apbmisc_base)
+               pr_err("failed to map APBMISC registers\n");
+
+       strapping_base = ioremap_nocache(straps.start, resource_size(&straps));
        if (!strapping_base)
-               pr_err("ioremap tegra strapping_base failed\n");
+               pr_err("failed to map strapping options registers\n");
+
+       long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
 }