These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / soc / tegra / fuse / speedo-tegra30.c

diff --git a/kernel/drivers/soc/tegra/fuse/speedo-tegra30.c b/kernel/drivers/soc/tegra/fuse/speedo-tegra30.c
index b17f0dc..9b010b3 100644 (file)
--- a/kernel/drivers/soc/tegra/fuse/speedo-tegra30.c
+++ b/kernel/drivers/soc/tegra/fuse/speedo-tegra30.c
@@ -22,7 +22,7 @@
 
 #include "fuse.h"
 
-#define CORE_PROCESS_CORNERS   1
+#define SOC_PROCESS_CORNERS    1
 #define CPU_PROCESS_CORNERS    6
 
 #define FUSE_SPEEDO_CALIB_0    0x14
@@ -54,7 +54,7 @@ enum {
        THRESHOLD_INDEX_COUNT,
 };
 
-static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
+static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
        {180},
        {170},
        {195},
@@ -93,25 +93,25 @@ static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
        int bit_minus1;
        int bit_minus2;
 
-       reg = tegra30_fuse_readl(FUSE_SPEEDO_CALIB_0);
+       reg = tegra_fuse_read_early(FUSE_SPEEDO_CALIB_0);
 
        *speedo_lp = (reg & 0xFFFF) * 4;
        *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
 
-       ate_ver = tegra30_fuse_readl(FUSE_TEST_PROG_VER);
+       ate_ver = tegra_fuse_read_early(FUSE_TEST_PROG_VER);
        pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10);
 
        if (ate_ver >= 26) {
-               bit_minus1 = tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS1);
-               bit_minus1 |= tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
-               bit_minus2 = tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS2);
-               bit_minus2 |= tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
+               bit_minus1 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1);
+               bit_minus1 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1_R);
+               bit_minus2 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2);
+               bit_minus2 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2_R);
                *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
 
-               bit_minus1 = tegra30_spare_fuse(G_SPEEDO_BIT_MINUS1);
-               bit_minus1 |= tegra30_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
-               bit_minus2 = tegra30_spare_fuse(G_SPEEDO_BIT_MINUS2);
-               bit_minus2 |= tegra30_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
+               bit_minus1 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1);
+               bit_minus1 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1_R);
+               bit_minus2 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2);
+               bit_minus2 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2_R);
                *speedo_g |= (bit_minus1 << 1) | bit_minus2;
        } else {
                *speedo_lp |= 0x3;
@@ -121,7 +121,7 @@ static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
 
 static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
 {
-       int package_id = tegra30_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
+       int package_id = tegra_fuse_read_early(FUSE_PACKAGE_INFO) & 0x0F;
 
        switch (sku_info->revision) {
        case TEGRA_REVISION_A01:
@@ -246,19 +246,19 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
 void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
 {
        u32 cpu_speedo_val;
-       u32 core_speedo_val;
+       u32 soc_speedo_val;
        int i;
 
        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
                        THRESHOLD_INDEX_COUNT);
-       BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+       BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
                        THRESHOLD_INDEX_COUNT);
 
 
        rev_sku_to_speedo_ids(sku_info);
-       fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
+       fuse_speedo_calib(&cpu_speedo_val, &soc_speedo_val);
        pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val);
-       pr_debug("Tegra Core speedo value %u\n", core_speedo_val);
+       pr_debug("Tegra Core speedo value %u\n", soc_speedo_val);
 
        for (i = 0; i < CPU_PROCESS_CORNERS; i++) {
                if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
@@ -273,16 +273,16 @@ void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
                sku_info->cpu_speedo_id = 1;
        }
 
-       for (i = 0; i < CORE_PROCESS_CORNERS; i++) {
-               if (core_speedo_val < core_process_speedos[threshold_index][i])
+       for (i = 0; i < SOC_PROCESS_CORNERS; i++) {
+               if (soc_speedo_val < soc_process_speedos[threshold_index][i])
                        break;
        }
-       sku_info->core_process_id = i - 1;
+       sku_info->soc_process_id = i - 1;
 
-       if (sku_info->core_process_id == -1) {
-               pr_warn("Tegra CORE speedo value %3d out of range",
-                                core_speedo_val);
-               sku_info->core_process_id = 0;
+       if (sku_info->soc_process_id == -1) {
+               pr_warn("Tegra SoC speedo value %3d out of range",
+                       soc_speedo_val);
+               sku_info->soc_process_id = 0;
                sku_info->soc_speedo_id = 1;
        }
 }