These changes are a raw update to a vanilla kernel 4.1.10, with the

[kvmfornfv.git] / kernel / drivers / pci / quirks.c

diff --git a/kernel/drivers/pci/quirks.c b/kernel/drivers/pci/quirks.c
index c6dc1df..804cd3b 100644 (file)
--- a/kernel/drivers/pci/quirks.c
+++ b/kernel/drivers/pci/quirks.c
@@ -1576,6 +1576,18 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB3
 
 #endif
 
+static void quirk_jmicron_async_suspend(struct pci_dev *dev)
+{
+       if (dev->multifunction) {
+               device_disable_async_suspend(&dev->dev);
+               dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
+       }
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
+
 #ifdef CONFIG_X86_IO_APIC
 static void quirk_alder_ioapic(struct pci_dev *pdev)
 {
@@ -1903,6 +1915,15 @@ static void quirk_netmos(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
                         PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
 
+static void quirk_f0_vpd_link(struct pci_dev *dev)
+{
+       if (!dev->multifunction || !PCI_FUNC(dev->devfn))
+               return;
+       dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
+}
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
+                             PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
+
 static void quirk_e100_interrupt(struct pci_dev *dev)
 {
        u16 command, pmcsr;
@@ -2838,12 +2859,15 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
 
 static void fixup_ti816x_class(struct pci_dev *dev)
 {
+       u32 class = dev->class;
+
        /* TI 816x devices do not have class code set when in PCIe boot mode */
-       dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
-       dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
+       dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
+       dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
+                class, dev->class);
 }
 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
-                                PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
+                             PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
 
 /* Some PCIe devices do not work reliably with the claimed maximum
  * payload size supported.