These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / net / ethernet / mellanox / mlx5 / core / en_txrx.c

diff --git a/kernel/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c b/kernel/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c
new file mode 100644 (file)
index 0000000..2c7cb67
--- /dev/null
+++ b/kernel/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "en.h"
+
+struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq)
+{
+       struct mlx5_cqwq *wq = &cq->wq;
+       u32 ci = mlx5_cqwq_get_ci(wq);
+       struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
+       int cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK;
+       int sw_ownership_val = mlx5_cqwq_get_wrap_cnt(wq) & 1;
+
+       if (cqe_ownership_bit != sw_ownership_val)
+               return NULL;
+
+       /* ensure cqe content is read after cqe ownership bit */
+       rmb();
+
+       return cqe;
+}
+
+int mlx5e_napi_poll(struct napi_struct *napi, int budget)
+{
+       struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,
+                                              napi);
+       bool busy = false;
+       int i;
+
+       clear_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
+
+       for (i = 0; i < c->num_tc; i++)
+               busy |= mlx5e_poll_tx_cq(&c->sq[i].cq);
+
+       busy |= mlx5e_poll_rx_cq(&c->rq.cq, budget);
+
+       busy |= mlx5e_post_rx_wqes(&c->rq);
+
+       if (busy)
+               return budget;
+
+       napi_complete(napi);
+
+       /* avoid losing completion event during/after polling cqs */
+       if (test_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags)) {
+               napi_schedule(napi);
+               return 0;
+       }
+
+       for (i = 0; i < c->num_tc; i++)
+               mlx5e_cq_arm(&c->sq[i].cq);
+       mlx5e_cq_arm(&c->rq.cq);
+
+       return 0;
+}
+
+void mlx5e_completion_event(struct mlx5_core_cq *mcq)
+{
+       struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
+
+       set_bit(MLX5E_CQ_HAS_CQES, &cq->flags);
+       set_bit(MLX5E_CHANNEL_NAPI_SCHED, &cq->channel->flags);
+       barrier();
+       napi_schedule(cq->napi);
+}
+
+void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event)
+{
+       struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
+       struct mlx5e_channel *c = cq->channel;
+       struct mlx5e_priv *priv = c->priv;
+       struct net_device *netdev = priv->netdev;
+
+       netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n",
+                  __func__, mcq->cqn, event);
+}