These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / net / ethernet / chelsio / cxgb4 / t4fw_api.h

diff --git a/kernel/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/kernel/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index 03fbfd1..a32de30 100644 (file)
--- a/kernel/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/kernel/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -762,8 +762,6 @@ enum fw_ldst_func_mod_index {
 
 struct fw_ldst_cmd {
        __be32 op_to_addrspace;
-#define FW_LDST_CMD_ADDRSPACE_S                0
-#define FW_LDST_CMD_ADDRSPACE_V(x)     ((x) << FW_LDST_CMD_ADDRSPACE_S)
        __be32 cycles_to_len16;
        union fw_ldst {
                struct fw_ldst_addrval {
@@ -772,7 +770,7 @@ struct fw_ldst_cmd {
                } addrval;
                struct fw_ldst_idctxt {
                        __be32 physid;
-                       __be32 msg_pkd;
+                       __be32 msg_ctxtflush;
                        __be32 ctxt_data7;
                        __be32 ctxt_data6;
                        __be32 ctxt_data5;
@@ -788,15 +786,34 @@ struct fw_ldst_cmd {
                        __be16 vctl;
                        __be16 rval;
                } mdio;
-               struct fw_ldst_mps {
-                       __be16 fid_ctl;
-                       __be16 rplcpf_pkd;
-                       __be32 rplc127_96;
-                       __be32 rplc95_64;
-                       __be32 rplc63_32;
-                       __be32 rplc31_0;
-                       __be32 atrb;
-                       __be16 vlan[16];
+               struct fw_ldst_cim_rq {
+                       u8 req_first64[8];
+                       u8 req_second64[8];
+                       u8 resp_first64[8];
+                       u8 resp_second64[8];
+                       __be32 r3[2];
+               } cim_rq;
+               union fw_ldst_mps {
+                       struct fw_ldst_mps_rplc {
+                               __be16 fid_idx;
+                               __be16 rplcpf_pkd;
+                               __be32 rplc255_224;
+                               __be32 rplc223_192;
+                               __be32 rplc191_160;
+                               __be32 rplc159_128;
+                               __be32 rplc127_96;
+                               __be32 rplc95_64;
+                               __be32 rplc63_32;
+                               __be32 rplc31_0;
+                       } rplc;
+                       struct fw_ldst_mps_atrb {
+                               __be16 fid_mpsid;
+                               __be16 r2[3];
+                               __be32 r3[2];
+                               __be32 r4;
+                               __be32 atrb;
+                               __be16 vlan[16];
+                       } atrb;
                } mps;
                struct fw_ldst_func {
                        u8 access_ctl;
@@ -816,12 +833,40 @@ struct fw_ldst_cmd {
                        __be16 nset_pkd;
                        __be32 data[12];
                } pcie;
+               struct fw_ldst_i2c_deprecated {
+                       u8 pid_pkd;
+                       u8 base;
+                       u8 boffset;
+                       u8 data;
+                       __be32 r9;
+               } i2c_deprecated;
+               struct fw_ldst_i2c {
+                       u8 pid;
+                       u8 did;
+                       u8 boffset;
+                       u8 blen;
+                       __be32 r9;
+                       __u8   data[48];
+               } i2c;
+               struct fw_ldst_le {
+                       __be32 index;
+                       __be32 r9;
+                       u8 val[33];
+                       u8 r11[7];
+               } le;
        } u;
 };
 
+#define FW_LDST_CMD_ADDRSPACE_S                0
+#define FW_LDST_CMD_ADDRSPACE_V(x)     ((x) << FW_LDST_CMD_ADDRSPACE_S)
+
 #define FW_LDST_CMD_MSG_S       31
 #define FW_LDST_CMD_MSG_V(x)   ((x) << FW_LDST_CMD_MSG_S)
 
+#define FW_LDST_CMD_CTXTFLUSH_S                30
+#define FW_LDST_CMD_CTXTFLUSH_V(x)     ((x) << FW_LDST_CMD_CTXTFLUSH_S)
+#define FW_LDST_CMD_CTXTFLUSH_F                FW_LDST_CMD_CTXTFLUSH_V(1U)
+
 #define FW_LDST_CMD_PADDR_S     8
 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S)
 
@@ -831,8 +876,8 @@ struct fw_ldst_cmd {
 #define FW_LDST_CMD_FID_S       15
 #define FW_LDST_CMD_FID_V(x)   ((x) << FW_LDST_CMD_FID_S)
 
-#define FW_LDST_CMD_CTL_S       0
-#define FW_LDST_CMD_CTL_V(x)   ((x) << FW_LDST_CMD_CTL_S)
+#define FW_LDST_CMD_IDX_S      0
+#define FW_LDST_CMD_IDX_V(x)   ((x) << FW_LDST_CMD_IDX_S)
 
 #define FW_LDST_CMD_RPLCPF_S    0
 #define FW_LDST_CMD_RPLCPF_V(x)        ((x) << FW_LDST_CMD_RPLCPF_S)
@@ -1061,6 +1106,7 @@ enum fw_params_param_dev {
        FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
        FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
        FW_PARAMS_PARAM_DEV_CF = 0x0D,
+       FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
        FW_PARAMS_PARAM_DEV_DIAG = 0x11,
        FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
        FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
@@ -1123,6 +1169,12 @@ enum fw_params_param_dmaq {
        FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
        FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
        FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
+       FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
+};
+
+enum fw_params_param_dev_phyfw {
+       FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
+       FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
 };
 
 enum fw_params_param_dev_diag {
@@ -1377,6 +1429,7 @@ struct fw_iq_cmd {
 
 #define FW_IQ_CMD_IQFLINTCONGEN_S      27
 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)   ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
+#define FW_IQ_CMD_IQFLINTCONGEN_F      FW_IQ_CMD_IQFLINTCONGEN_V(1U)
 
 #define FW_IQ_CMD_IQFLINTISCSIC_S      26
 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)   ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
@@ -1399,6 +1452,7 @@ struct fw_iq_cmd {
 
 #define FW_IQ_CMD_FL0CONGCIF_S         11
 #define FW_IQ_CMD_FL0CONGCIF_V(x)      ((x) << FW_IQ_CMD_FL0CONGCIF_S)
+#define FW_IQ_CMD_FL0CONGCIF_F         FW_IQ_CMD_FL0CONGCIF_V(1U)
 
 #define FW_IQ_CMD_FL0ONCHIP_S          10
 #define FW_IQ_CMD_FL0ONCHIP_V(x)       ((x) << FW_IQ_CMD_FL0ONCHIP_S)
@@ -1589,6 +1643,7 @@ struct fw_eq_eth_cmd {
 
 #define FW_EQ_ETH_CMD_FETCHRO_S                22
 #define FW_EQ_ETH_CMD_FETCHRO_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
+#define FW_EQ_ETH_CMD_FETCHRO_F                FW_EQ_ETH_CMD_FETCHRO_V(1U)
 
 #define FW_EQ_ETH_CMD_HOSTFCMODE_S     20
 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
@@ -2526,13 +2581,8 @@ enum fw_port_mod_sub_type {
        FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
 };
 
-/* port stats */
-#define FW_NUM_PORT_STATS 50
-#define FW_NUM_PORT_TX_STATS 23
-#define FW_NUM_PORT_RX_STATS 27
-
 enum fw_port_stats_tx_index {
-       FW_STAT_TX_PORT_BYTES_IX,
+       FW_STAT_TX_PORT_BYTES_IX = 0,
        FW_STAT_TX_PORT_FRAMES_IX,
        FW_STAT_TX_PORT_BCAST_IX,
        FW_STAT_TX_PORT_MCAST_IX,
@@ -2554,11 +2604,12 @@ enum fw_port_stats_tx_index {
        FW_STAT_TX_PORT_PPP4_IX,
        FW_STAT_TX_PORT_PPP5_IX,
        FW_STAT_TX_PORT_PPP6_IX,
-       FW_STAT_TX_PORT_PPP7_IX
+       FW_STAT_TX_PORT_PPP7_IX,
+       FW_NUM_PORT_TX_STATS
 };
 
 enum fw_port_stat_rx_index {
-       FW_STAT_RX_PORT_BYTES_IX,
+       FW_STAT_RX_PORT_BYTES_IX = 0,
        FW_STAT_RX_PORT_FRAMES_IX,
        FW_STAT_RX_PORT_BCAST_IX,
        FW_STAT_RX_PORT_MCAST_IX,
@@ -2584,9 +2635,14 @@ enum fw_port_stat_rx_index {
        FW_STAT_RX_PORT_PPP5_IX,
        FW_STAT_RX_PORT_PPP6_IX,
        FW_STAT_RX_PORT_PPP7_IX,
-       FW_STAT_RX_PORT_LESS_64B_IX
+       FW_STAT_RX_PORT_LESS_64B_IX,
+       FW_STAT_RX_PORT_MAC_ERROR_IX,
+       FW_NUM_PORT_RX_STATS
 };
 
+/* port stats */
+#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
+
 struct fw_port_stats_cmd {
        __be32 op_to_portid;
        __be32 retval_len16;
@@ -3015,7 +3071,8 @@ struct fw_hdr {
 
 enum fw_hdr_chip {
        FW_HDR_CHIP_T4,
-       FW_HDR_CHIP_T5
+       FW_HDR_CHIP_T5,
+       FW_HDR_CHIP_T6
 };
 
 #define FW_HDR_FW_VER_MAJOR_S  24