These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / gpu / ipu-v3 / ipu-di.c

diff --git a/kernel/drivers/gpu/ipu-v3/ipu-di.c b/kernel/drivers/gpu/ipu-v3/ipu-di.c
index 2970c6b..359268e 100644 (file)
--- a/kernel/drivers/gpu/ipu-v3/ipu-di.c
+++ b/kernel/drivers/gpu/ipu-v3/ipu-di.c
@@ -71,6 +71,10 @@ enum di_sync_wave {
        DI_SYNC_HSYNC = 3,
        DI_SYNC_VSYNC = 4,
        DI_SYNC_DE = 6,
+
+       DI_SYNC_CNT1 = 2,       /* counter >= 2 only */
+       DI_SYNC_CNT4 = 5,       /* counter >= 5 only */
+       DI_SYNC_CNT5 = 6,       /* counter >= 6 only */
 };
 
 #define SYNC_WAVE 0
@@ -211,66 +215,59 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
                sig->mode.hback_porch + sig->mode.hfront_porch;
        u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
                sig->mode.vback_porch + sig->mode.vfront_porch;
-       u32 reg;
        struct di_sync_config cfg[] = {
                {
-                       .run_count = h_total / 2 - 1,
-                       .run_src = DI_SYNC_CLK,
+                       /* 1: internal VSYNC for each frame */
+                       .run_count = v_total * 2 - 1,
+                       .run_src = 3,                   /* == counter 7 */
                }, {
-                       .run_count = h_total - 11,
+                       /* PIN2: HSYNC waveform */
+                       .run_count = h_total - 1,
                        .run_src = DI_SYNC_CLK,
-                       .cnt_down = 4,
+                       .cnt_polarity_gen_en = 1,
+                       .cnt_polarity_trigger_src = DI_SYNC_CLK,
+                       .cnt_down = sig->mode.hsync_len * 2,
                }, {
-                       .run_count = v_total * 2 - 1,
-                       .run_src = DI_SYNC_INT_HSYNC,
-                       .offset_count = 1,
-                       .offset_src = DI_SYNC_INT_HSYNC,
-                       .cnt_down = 4,
+                       /* PIN3: VSYNC waveform */
+                       .run_count = v_total - 1,
+                       .run_src = 4,                   /* == counter 7 */
+                       .cnt_polarity_gen_en = 1,
+                       .cnt_polarity_trigger_src = 4,  /* == counter 7 */
+                       .cnt_down = sig->mode.vsync_len * 2,
+                       .cnt_clr_src = DI_SYNC_CNT1,
                }, {
-                       .run_count = v_total / 2 - 1,
+                       /* 4: Field */
+                       .run_count = v_total / 2,
                        .run_src = DI_SYNC_HSYNC,
-                       .offset_count = sig->mode.vback_porch,
-                       .offset_src = DI_SYNC_HSYNC,
+                       .offset_count = h_total / 2,
+                       .offset_src = DI_SYNC_CLK,
                        .repeat_count = 2,
-                       .cnt_clr_src = DI_SYNC_VSYNC,
-               }, {
-                       .run_src = DI_SYNC_HSYNC,
-                       .repeat_count = sig->mode.vactive / 2,
-                       .cnt_clr_src = 4,
-               }, {
-                       .run_count = v_total - 1,
-                       .run_src = DI_SYNC_HSYNC,
+                       .cnt_clr_src = DI_SYNC_CNT1,
                }, {
-                       .run_count = v_total / 2 - 1,
+                       /* 5: Active lines */
                        .run_src = DI_SYNC_HSYNC,
-                       .offset_count = 9,
+                       .offset_count = (sig->mode.vsync_len +
+                                        sig->mode.vback_porch) / 2,
                        .offset_src = DI_SYNC_HSYNC,
-                       .repeat_count = 2,
-                       .cnt_clr_src = DI_SYNC_VSYNC,
+                       .repeat_count = sig->mode.vactive / 2,
+                       .cnt_clr_src = DI_SYNC_CNT4,
                }, {
+                       /* 6: Active pixel, referenced by DC */
                        .run_src = DI_SYNC_CLK,
-                       .offset_count = sig->mode.hback_porch,
+                       .offset_count = sig->mode.hsync_len +
+                                       sig->mode.hback_porch,
                        .offset_src = DI_SYNC_CLK,
                        .repeat_count = sig->mode.hactive,
-                       .cnt_clr_src = 5,
+                       .cnt_clr_src = DI_SYNC_CNT5,
                }, {
-                       .run_count = v_total - 1,
-                       .run_src = DI_SYNC_INT_HSYNC,
-                       .offset_count = v_total / 2,
-                       .offset_src = DI_SYNC_INT_HSYNC,
-                       .cnt_clr_src = DI_SYNC_HSYNC,
-                       .cnt_down = 4,
+                       /* 7: Half line HSYNC */
+                       .run_count = h_total / 2 - 1,
+                       .run_src = DI_SYNC_CLK,
                }
        };
 
        ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
 
-       /* set gentime select and tag sel */
-       reg = ipu_di_read(di, DI_SW_GEN1(9));
-       reg &= 0x1FFFFFFF;
-       reg |= (3 - 1) << 29 | 0x00008000;
-       ipu_di_write(di, reg, DI_SW_GEN1(9));
-
        ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF);
 }
 
@@ -543,6 +540,29 @@ int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode)
 }
 EXPORT_SYMBOL_GPL(ipu_di_adjust_videomode);
 
+static u32 ipu_di_gen_polarity(int pin)
+{
+       switch (pin) {
+       case 1:
+               return DI_GEN_POLARITY_1;
+       case 2:
+               return DI_GEN_POLARITY_2;
+       case 3:
+               return DI_GEN_POLARITY_3;
+       case 4:
+               return DI_GEN_POLARITY_4;
+       case 5:
+               return DI_GEN_POLARITY_5;
+       case 6:
+               return DI_GEN_POLARITY_6;
+       case 7:
+               return DI_GEN_POLARITY_7;
+       case 8:
+               return DI_GEN_POLARITY_8;
+       }
+       return 0;
+}
+
 int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 {
        u32 reg;
@@ -582,15 +602,8 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 
                /* set y_sel = 1 */
                di_gen |= 0x10000000;
-               di_gen |= DI_GEN_POLARITY_5;
-               di_gen |= DI_GEN_POLARITY_8;
-
-               vsync_cnt = 7;
 
-               if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH)
-                       di_gen |= DI_GEN_POLARITY_3;
-               if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH)
-                       di_gen |= DI_GEN_POLARITY_2;
+               vsync_cnt = 3;
        } else {
                ipu_di_sync_config_noninterlaced(di, sig, div);
 
@@ -602,25 +615,13 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
                         */
                        if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
                                vsync_cnt = 6;
-
-               if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH) {
-                       if (sig->hsync_pin == 2)
-                               di_gen |= DI_GEN_POLARITY_2;
-                       else if (sig->hsync_pin == 4)
-                               di_gen |= DI_GEN_POLARITY_4;
-                       else if (sig->hsync_pin == 7)
-                               di_gen |= DI_GEN_POLARITY_7;
-               }
-               if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH) {
-                       if (sig->vsync_pin == 3)
-                               di_gen |= DI_GEN_POLARITY_3;
-                       else if (sig->vsync_pin == 6)
-                               di_gen |= DI_GEN_POLARITY_6;
-                       else if (sig->vsync_pin == 8)
-                               di_gen |= DI_GEN_POLARITY_8;
-               }
        }
 
+       if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH)
+               di_gen |= ipu_di_gen_polarity(sig->hsync_pin);
+       if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH)
+               di_gen |= ipu_di_gen_polarity(sig->vsync_pin);
+
        if (sig->clk_pol)
                di_gen |= DI_GEN_POLARITY_DISP_CLK;