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These changes are the raw update to linux-4.4.6-rt14. Kernel sources
[kvmfornfv.git]
/
kernel
/
drivers
/
gpu
/
drm
/
radeon
/
vce_v2_0.c
diff --git
a/kernel/drivers/gpu/drm/radeon/vce_v2_0.c
b/kernel/drivers/gpu/drm/radeon/vce_v2_0.c
index
fbbe78f
..
cdeaab7
100644
(file)
--- a/
kernel/drivers/gpu/drm/radeon/vce_v2_0.c
+++ b/
kernel/drivers/gpu/drm/radeon/vce_v2_0.c
@@
-31,6
+31,10
@@
#include "radeon_asic.h"
#include "cikd.h"
#include "radeon_asic.h"
#include "cikd.h"
+#define VCE_V2_0_FW_SIZE (256 * 1024)
+#define VCE_V2_0_STACK_SIZE (64 * 1024)
+#define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES)
+
static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
{
u32 tmp;
static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
{
u32 tmp;
@@
-140,6
+144,12
@@
static void vce_v2_0_init_cg(struct radeon_device *rdev)
WREG32(VCE_CLOCK_GATING_B, tmp);
}
WREG32(VCE_CLOCK_GATING_B, tmp);
}
+unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
+{
+ WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
+ return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
+}
+
int vce_v2_0_resume(struct radeon_device *rdev)
{
uint64_t addr = rdev->vce.gpu_addr;
int vce_v2_0_resume(struct radeon_device *rdev)
{
uint64_t addr = rdev->vce.gpu_addr;
@@
-159,17
+169,17
@@
int vce_v2_0_resume(struct radeon_device *rdev)
WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
addr &= 0xff;
WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
addr &= 0xff;
- size =
RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size)
;
+ size =
VCE_V2_0_FW_SIZE
;
WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
WREG32(VCE_VCPU_CACHE_SIZE0, size);
addr += size;
WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
WREG32(VCE_VCPU_CACHE_SIZE0, size);
addr += size;
- size =
RADEON_VCE
_STACK_SIZE;
+ size =
VCE_V2_0
_STACK_SIZE;
WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
WREG32(VCE_VCPU_CACHE_SIZE1, size);
addr += size;
WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
WREG32(VCE_VCPU_CACHE_SIZE1, size);
addr += size;
- size =
RADEON_VCE_HEAP
_SIZE;
+ size =
VCE_V2_0_DATA
_SIZE;
WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
WREG32(VCE_VCPU_CACHE_SIZE2, size);
WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
WREG32(VCE_VCPU_CACHE_SIZE2, size);