These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / gpu / drm / radeon / sid.h

diff --git a/kernel/drivers/gpu/drm/radeon/sid.h b/kernel/drivers/gpu/drm/radeon/sid.h
index 3afac30..d1a7b58 100644 (file)
--- a/kernel/drivers/gpu/drm/radeon/sid.h
+++ b/kernel/drivers/gpu/drm/radeon/sid.h
@@ -915,6 +915,11 @@
 #define DCCG_AUDIO_DTO1_PHASE                           0x05c0
 #define DCCG_AUDIO_DTO1_MODULE                          0x05c4
 
+#define DENTIST_DISPCLK_CNTL                           0x0490
+#      define DENTIST_DPREFCLK_WDIVIDER(x)             (((x) & 0x7f) << 24)
+#      define DENTIST_DPREFCLK_WDIVIDER_MASK           (0x7f << 24)
+#      define DENTIST_DPREFCLK_WDIVIDER_SHIFT          24
+
 #define AFMT_AUDIO_SRC_CONTROL                          0x713c
 #define                AFMT_AUDIO_SRC_SELECT(x)                (((x) & 7) << 0)
 /* AFMT_AUDIO_SRC_SELECT
@@ -1879,6 +1884,7 @@
 #define VCE_VCPU_CACHE_SIZE1                           0x20030
 #define VCE_VCPU_CACHE_OFFSET2                         0x20034
 #define VCE_VCPU_CACHE_SIZE2                           0x20038
+#define VCE_VCPU_SCRATCH7                              0x200dc
 #define VCE_SOFT_RESET                                 0x20120
 #define        VCE_ECPU_SOFT_RESET                     (1 << 0)
 #define        VCE_FME_SOFT_RESET                      (1 << 2)
@@ -1893,6 +1899,7 @@
 #define VCE_RB_RPTR                                    0x2018c
 #define VCE_RB_WPTR                                    0x20190
 #define VCE_CLOCK_GATING_A                             0x202f8
+#      define CGC_DYN_CLOCK_MODE                       (1 << 16)
 #define VCE_CLOCK_GATING_B                             0x202fc
 #define VCE_UENC_CLOCK_GATING                          0x205bc
 #define VCE_UENC_REG_CLOCK_GATING                      0x205c0
@@ -1917,4 +1924,31 @@
 #define VCE_CMD_IB_AUTO                                        0x00000005
 #define VCE_CMD_SEMAPHORE                              0x00000006
 
+/* discrete vce clocks */
+#define        CG_VCEPLL_FUNC_CNTL                             0xc0030600
+#      define VCEPLL_RESET_MASK                        0x00000001
+#      define VCEPLL_SLEEP_MASK                        0x00000002
+#      define VCEPLL_BYPASS_EN_MASK                    0x00000004
+#      define VCEPLL_CTLREQ_MASK                       0x00000008
+#      define VCEPLL_VCO_MODE_MASK                     0x00000600
+#      define VCEPLL_REF_DIV_MASK                      0x003F0000
+#      define VCEPLL_CTLACK_MASK                       0x40000000
+#      define VCEPLL_CTLACK2_MASK                      0x80000000
+#define        CG_VCEPLL_FUNC_CNTL_2                           0xc0030601
+#      define VCEPLL_PDIV_A(x)                         ((x) << 0)
+#      define VCEPLL_PDIV_A_MASK                       0x0000007F
+#      define VCEPLL_PDIV_B(x)                         ((x) << 8)
+#      define VCEPLL_PDIV_B_MASK                       0x00007F00
+#      define EVCLK_SRC_SEL(x)                         ((x) << 20)
+#      define EVCLK_SRC_SEL_MASK                       0x01F00000
+#      define ECCLK_SRC_SEL(x)                         ((x) << 25)
+#      define ECCLK_SRC_SEL_MASK                       0x3E000000
+#define        CG_VCEPLL_FUNC_CNTL_3                           0xc0030602
+#      define VCEPLL_FB_DIV(x)                         ((x) << 0)
+#      define VCEPLL_FB_DIV_MASK                       0x01FFFFFF
+#define        CG_VCEPLL_FUNC_CNTL_4                           0xc0030603
+#define        CG_VCEPLL_FUNC_CNTL_5                           0xc0030604
+#define        CG_VCEPLL_SPREAD_SPECTRUM                       0xc0030606
+#      define VCEPLL_SSEN_MASK                         0x00000001
+
 #endif