These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / gpu / drm / radeon / r100.c

diff --git a/kernel/drivers/gpu/drm/radeon/r100.c b/kernel/drivers/gpu/drm/radeon/r100.c
index 04f2514..9e7e2bf 100644 (file)
--- a/kernel/drivers/gpu/drm/radeon/r100.c
+++ b/kernel/drivers/gpu/drm/radeon/r100.c
@@ -806,7 +806,7 @@ int r100_irq_process(struct radeon_device *rdev)
                status = r100_irq_ack(rdev);
        }
        if (queue_hotplug)
-               schedule_work(&rdev->hotplug_work);
+               schedule_delayed_work(&rdev->hotplug_work, 0);
        if (rdev->msi_enabled) {
                switch (rdev->family) {
                case CHIP_RS400:
@@ -3217,6 +3217,9 @@ void r100_bandwidth_update(struct radeon_device *rdev)
        uint32_t pixel_bytes1 = 0;
        uint32_t pixel_bytes2 = 0;
 
+       /* Guess line buffer size to be 8192 pixels */
+       u32 lb_size = 8192;
+
        if (!rdev->mode_info.mode_config_initialized)
                return;
 
@@ -3631,6 +3634,13 @@ void r100_bandwidth_update(struct radeon_device *rdev)
                DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
                          (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
        }
+
+       /* Save number of lines the linebuffer leads before the scanout */
+       if (mode1)
+           rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
+
+       if (mode2)
+           rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
 }
 
 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
@@ -4090,6 +4100,28 @@ int r100_init(struct radeon_device *rdev)
        return 0;
 }
 
+uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
+{
+       unsigned long flags;
+       uint32_t ret;
+
+       spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
+       writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
+       ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
+       spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
+       return ret;
+}
+
+void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
+       writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
+       writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
+       spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
+}
+
 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
 {
        if (reg < rdev->rio_mem_size)