These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / gpu / drm / radeon / cik_reg.h

diff --git a/kernel/drivers/gpu/drm/radeon/cik_reg.h b/kernel/drivers/gpu/drm/radeon/cik_reg.h
index f667347..4e883fd 100644 (file)
--- a/kernel/drivers/gpu/drm/radeon/cik_reg.h
+++ b/kernel/drivers/gpu/drm/radeon/cik_reg.h
@@ -149,8 +149,30 @@
 
 #define KFD_CIK_SDMA_QUEUE_OFFSET              0x200
 
+#define SQ_IND_INDEX                                   0x8DE0
+#define SQ_CMD                                         0x8DEC
+#define SQ_IND_DATA                                    0x8DE4
+
+/*
+ * The TCP_WATCHx_xxxx addresses that are shown here are in dwords,
+ * and that's why they are multiplied by 4
+ */
+#define TCP_WATCH0_ADDR_H                              (0x32A0*4)
+#define TCP_WATCH1_ADDR_H                              (0x32A3*4)
+#define TCP_WATCH2_ADDR_H                              (0x32A6*4)
+#define TCP_WATCH3_ADDR_H                              (0x32A9*4)
+#define TCP_WATCH0_ADDR_L                              (0x32A1*4)
+#define TCP_WATCH1_ADDR_L                              (0x32A4*4)
+#define TCP_WATCH2_ADDR_L                              (0x32A7*4)
+#define TCP_WATCH3_ADDR_L                              (0x32AA*4)
+#define TCP_WATCH0_CNTL                                        (0x32A2*4)
+#define TCP_WATCH1_CNTL                                        (0x32A5*4)
+#define TCP_WATCH2_CNTL                                        (0x32A8*4)
+#define TCP_WATCH3_CNTL                                        (0x32AB*4)
+
+#define CPC_INT_CNTL                                   0xC2D0
+
 #define CP_HQD_IQ_RPTR                                 0xC970u
-#define AQL_ENABLE                                     (1U << 0)
 #define SDMA0_RLC0_RB_CNTL                             0xD400u
 #define        SDMA_RB_VMID(x)                                 (x << 24)
 #define        SDMA0_RLC0_RB_BASE                              0xD404u
@@ -184,4 +206,38 @@
 #define        SDMA0_CNTL                                      0xD010
 #define        SDMA1_CNTL                                      0xD810
 
+enum {
+       MAX_TRAPID = 8,         /* 3 bits in the bitfield.  */
+       MAX_WATCH_ADDRESSES = 4
+};
+
+enum {
+       ADDRESS_WATCH_REG_ADDR_HI = 0,
+       ADDRESS_WATCH_REG_ADDR_LO,
+       ADDRESS_WATCH_REG_CNTL,
+       ADDRESS_WATCH_REG_MAX
+};
+
+enum {                         /*  not defined in the CI/KV reg file  */
+       ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
+       ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
+       ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
+       /* extend the mask to 26 bits in order to match the low address field */
+       ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
+       ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
+};
+
+union TCP_WATCH_CNTL_BITS {
+       struct {
+               uint32_t mask:24;
+               uint32_t vmid:4;
+               uint32_t atc:1;
+               uint32_t mode:2;
+               uint32_t valid:1;
+       } bitfields, bits;
+       uint32_t u32All;
+       signed int i32All;
+       float f32All;
+};
+
 #endif