These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / gpu / drm / nouveau / nvkm / subdev / mmu / nv04.c

diff --git a/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
index fe93ea2..37927c3 100644 (file)
--- a/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
+++ b/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
@@ -23,7 +23,6 @@
  */
 #include "nv04.h"
 
-#include <core/device.h>
 #include <core/gpuobj.h>
 
 #define NV04_PDMA_SIZE (128 * 1024 * 1024)
@@ -34,30 +33,34 @@
  ******************************************************************************/
 
 static void
-nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
+nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt,
               struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
 {
        pte = 0x00008 + (pte * 4);
+       nvkm_kmap(pgt);
        while (cnt) {
                u32 page = PAGE_SIZE / NV04_PDMA_PAGE;
                u32 phys = (u32)*list++;
                while (cnt && page--) {
-                       nv_wo32(pgt, pte, phys | 3);
+                       nvkm_wo32(pgt, pte, phys | 3);
                        phys += NV04_PDMA_PAGE;
                        pte += 4;
                        cnt -= 1;
                }
        }
+       nvkm_done(pgt);
 }
 
 static void
-nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
+nv04_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
 {
        pte = 0x00008 + (pte * 4);
+       nvkm_kmap(pgt);
        while (cnt--) {
-               nv_wo32(pgt, pte, 0x00000000);
+               nvkm_wo32(pgt, pte, 0x00000000);
                pte += 4;
        }
+       nvkm_done(pgt);
 }
 
 static void
@@ -65,87 +68,82 @@ nv04_vm_flush(struct nvkm_vm *vm)
 {
 }
 
-/*******************************************************************************
- * VM object
- ******************************************************************************/
-
-int
-nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart,
-              struct nvkm_vm **pvm)
-{
-       return -EINVAL;
-}
-
 /*******************************************************************************
  * MMU subdev
  ******************************************************************************/
 
 static int
-nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-             struct nvkm_oclass *oclass, void *data, u32 size,
-             struct nvkm_object **pobject)
+nv04_mmu_oneinit(struct nvkm_mmu *base)
 {
-       struct nv04_mmu_priv *priv;
-       struct nvkm_gpuobj *dma;
+       struct nv04_mmu *mmu = nv04_mmu(base);
+       struct nvkm_device *device = mmu->base.subdev.device;
+       struct nvkm_memory *dma;
        int ret;
 
-       ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART",
-                             "pcigart", &priv);
-       *pobject = nv_object(priv);
-       if (ret)
-               return ret;
-
-       priv->base.create = nv04_vm_create;
-       priv->base.limit = NV04_PDMA_SIZE;
-       priv->base.dma_bits = 32;
-       priv->base.pgt_bits = 32 - 12;
-       priv->base.spg_shift = 12;
-       priv->base.lpg_shift = 12;
-       priv->base.map_sg = nv04_vm_map_sg;
-       priv->base.unmap = nv04_vm_unmap;
-       priv->base.flush = nv04_vm_flush;
-
-       ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096,
-                            &priv->vm);
+       ret = nvkm_vm_create(&mmu->base, 0, NV04_PDMA_SIZE, 0, 4096, NULL,
+                            &mmu->vm);
        if (ret)
                return ret;
 
-       ret = nvkm_gpuobj_new(nv_object(priv), NULL,
+       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
                              (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8,
-                             16, NVOBJ_FLAG_ZERO_ALLOC,
-                             &priv->vm->pgt[0].obj[0]);
-       dma = priv->vm->pgt[0].obj[0];
-       priv->vm->pgt[0].refcount[0] = 1;
+                             16, true, &dma);
+       mmu->vm->pgt[0].mem[0] = dma;
+       mmu->vm->pgt[0].refcount[0] = 1;
        if (ret)
                return ret;
 
-       nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */
-       nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1);
+       nvkm_kmap(dma);
+       nvkm_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */
+       nvkm_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1);
+       nvkm_done(dma);
        return 0;
 }
 
-void
-nv04_mmu_dtor(struct nvkm_object *object)
+void *
+nv04_mmu_dtor(struct nvkm_mmu *base)
 {
-       struct nv04_mmu_priv *priv = (void *)object;
-       if (priv->vm) {
-               nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
-               nvkm_vm_ref(NULL, &priv->vm, NULL);
+       struct nv04_mmu *mmu = nv04_mmu(base);
+       struct nvkm_device *device = mmu->base.subdev.device;
+       if (mmu->vm) {
+               nvkm_memory_del(&mmu->vm->pgt[0].mem[0]);
+               nvkm_vm_ref(NULL, &mmu->vm, NULL);
        }
-       if (priv->nullp) {
-               pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
-                                   priv->nullp, priv->null);
+       if (mmu->nullp) {
+               dma_free_coherent(device->dev, 16 * 1024,
+                                 mmu->nullp, mmu->null);
        }
-       nvkm_mmu_destroy(&priv->base);
+       return mmu;
+}
+
+int
+nv04_mmu_new_(const struct nvkm_mmu_func *func, struct nvkm_device *device,
+             int index, struct nvkm_mmu **pmmu)
+{
+       struct nv04_mmu *mmu;
+       if (!(mmu = kzalloc(sizeof(*mmu), GFP_KERNEL)))
+               return -ENOMEM;
+       *pmmu = &mmu->base;
+       nvkm_mmu_ctor(func, device, index, &mmu->base);
+       return 0;
 }
 
-struct nvkm_oclass
-nv04_mmu_oclass = {
-       .handle = NV_SUBDEV(MMU, 0x04),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = nv04_mmu_ctor,
-               .dtor = nv04_mmu_dtor,
-               .init = _nvkm_mmu_init,
-               .fini = _nvkm_mmu_fini,
-       },
+const struct nvkm_mmu_func
+nv04_mmu = {
+       .oneinit = nv04_mmu_oneinit,
+       .dtor = nv04_mmu_dtor,
+       .limit = NV04_PDMA_SIZE,
+       .dma_bits = 32,
+       .pgt_bits = 32 - 12,
+       .spg_shift = 12,
+       .lpg_shift = 12,
+       .map_sg = nv04_vm_map_sg,
+       .unmap = nv04_vm_unmap,
+       .flush = nv04_vm_flush,
 };
+
+int
+nv04_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
+{
+       return nv04_mmu_new_(&nv04_mmu, device, index, pmmu);
+}