These changes are the raw update to linux-4.4.6-rt14. Kernel sources
[kvmfornfv.git] / kernel / drivers / gpu / drm / nouveau / nvkm / subdev / mc / nv50.c
index 40e3019..5f27d7b 100644 (file)
  *
  * Authors: Ben Skeggs
  */
-#include "nv04.h"
-
-#include <core/device.h>
+#include "priv.h"
 
 const struct nvkm_mc_intr
 nv50_mc_intr[] = {
-       { 0x04000000, NVDEV_ENGINE_DISP },  /* DISP before FIFO, so pageflip-timestamping works! */
-       { 0x00000001, NVDEV_ENGINE_MPEG },
-       { 0x00000100, NVDEV_ENGINE_FIFO },
-       { 0x00001000, NVDEV_ENGINE_GR },
-       { 0x00004000, NVDEV_ENGINE_CIPHER },    /* NV84- */
-       { 0x00008000, NVDEV_ENGINE_BSP },       /* NV84- */
-       { 0x00020000, NVDEV_ENGINE_VP },        /* NV84- */
-       { 0x00100000, NVDEV_SUBDEV_TIMER },
-       { 0x00200000, NVDEV_SUBDEV_GPIO },      /* PMGR->GPIO */
-       { 0x00200000, NVDEV_SUBDEV_I2C },       /* PMGR->I2C/AUX */
-       { 0x10000000, NVDEV_SUBDEV_BUS },
-       { 0x80000000, NVDEV_ENGINE_SW },
-       { 0x0002d101, NVDEV_SUBDEV_FB },
+       { 0x04000000, NVKM_ENGINE_DISP },  /* DISP before FIFO, so pageflip-timestamping works! */
+       { 0x00000001, NVKM_ENGINE_MPEG },
+       { 0x00000100, NVKM_ENGINE_FIFO },
+       { 0x00001000, NVKM_ENGINE_GR },
+       { 0x00004000, NVKM_ENGINE_CIPHER },     /* NV84- */
+       { 0x00008000, NVKM_ENGINE_BSP },        /* NV84- */
+       { 0x00020000, NVKM_ENGINE_VP }, /* NV84- */
+       { 0x00100000, NVKM_SUBDEV_TIMER },
+       { 0x00200000, NVKM_SUBDEV_GPIO },       /* PMGR->GPIO */
+       { 0x00200000, NVKM_SUBDEV_I2C },        /* PMGR->I2C/AUX */
+       { 0x10000000, NVKM_SUBDEV_BUS },
+       { 0x80000000, NVKM_ENGINE_SW },
+       { 0x0002d101, NVKM_SUBDEV_FB },
        {},
 };
 
-static void
-nv50_mc_msi_rearm(struct nvkm_mc *pmc)
+void
+nv50_mc_init(struct nvkm_mc *mc)
 {
-       struct nvkm_device *device = nv_device(pmc);
-       pci_write_config_byte(device->pdev, 0x68, 0xff);
+       struct nvkm_device *device = mc->subdev.device;
+       nvkm_wr32(device, 0x000200, 0xffffffff); /* everything on */
 }
 
+static const struct nvkm_mc_func
+nv50_mc = {
+       .init = nv50_mc_init,
+       .intr = nv50_mc_intr,
+       .intr_unarm = nv04_mc_intr_unarm,
+       .intr_rearm = nv04_mc_intr_rearm,
+       .intr_mask = nv04_mc_intr_mask,
+};
+
 int
-nv50_mc_init(struct nvkm_object *object)
+nv50_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
 {
-       struct nv04_mc_priv *priv = (void *)object;
-       nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */
-       return nvkm_mc_init(&priv->base);
+       return nvkm_mc_new_(&nv50_mc, device, index, pmc);
 }
-
-struct nvkm_oclass *
-nv50_mc_oclass = &(struct nvkm_mc_oclass) {
-       .base.handle = NV_SUBDEV(MC, 0x50),
-       .base.ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = nv04_mc_ctor,
-               .dtor = _nvkm_mc_dtor,
-               .init = nv50_mc_init,
-               .fini = _nvkm_mc_fini,
-       },
-       .intr = nv50_mc_intr,
-       .msi_rearm = nv50_mc_msi_rearm,
-}.base;