These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / gpu / drm / nouveau / nvkm / subdev / gpio / g94.c

diff --git a/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c b/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
index 12b3e01..6dcda55 100644 (file)
--- a/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
+++ b/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
@@ -26,21 +26,23 @@
 void
 g94_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
 {
-       u32 intr0 = nv_rd32(gpio, 0x00e054);
-       u32 intr1 = nv_rd32(gpio, 0x00e074);
-       u32 stat0 = nv_rd32(gpio, 0x00e050) & intr0;
-       u32 stat1 = nv_rd32(gpio, 0x00e070) & intr1;
+       struct nvkm_device *device = gpio->subdev.device;
+       u32 intr0 = nvkm_rd32(device, 0x00e054);
+       u32 intr1 = nvkm_rd32(device, 0x00e074);
+       u32 stat0 = nvkm_rd32(device, 0x00e050) & intr0;
+       u32 stat1 = nvkm_rd32(device, 0x00e070) & intr1;
        *lo = (stat1 & 0xffff0000) | (stat0 >> 16);
        *hi = (stat1 << 16) | (stat0 & 0x0000ffff);
-       nv_wr32(gpio, 0x00e054, intr0);
-       nv_wr32(gpio, 0x00e074, intr1);
+       nvkm_wr32(device, 0x00e054, intr0);
+       nvkm_wr32(device, 0x00e074, intr1);
 }
 
 void
 g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
 {
-       u32 inte0 = nv_rd32(gpio, 0x00e050);
-       u32 inte1 = nv_rd32(gpio, 0x00e070);
+       struct nvkm_device *device = gpio->subdev.device;
+       u32 inte0 = nvkm_rd32(device, 0x00e050);
+       u32 inte1 = nvkm_rd32(device, 0x00e070);
        if (type & NVKM_GPIO_LO)
                inte0 = (inte0 & ~(mask << 16)) | (data << 16);
        if (type & NVKM_GPIO_HI)
@@ -51,23 +53,22 @@ g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
                inte1 = (inte1 & ~(mask << 16)) | (data << 16);
        if (type & NVKM_GPIO_HI)
                inte1 = (inte1 & ~mask) | data;
-       nv_wr32(gpio, 0x00e050, inte0);
-       nv_wr32(gpio, 0x00e070, inte1);
+       nvkm_wr32(device, 0x00e050, inte0);
+       nvkm_wr32(device, 0x00e070, inte1);
 }
 
-struct nvkm_oclass *
-g94_gpio_oclass = &(struct nvkm_gpio_impl) {
-       .base.handle = NV_SUBDEV(GPIO, 0x94),
-       .base.ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = _nvkm_gpio_ctor,
-               .dtor = _nvkm_gpio_dtor,
-               .init = _nvkm_gpio_init,
-               .fini = _nvkm_gpio_fini,
-       },
+static const struct nvkm_gpio_func
+g94_gpio = {
        .lines = 32,
        .intr_stat = g94_gpio_intr_stat,
        .intr_mask = g94_gpio_intr_mask,
        .drive = nv50_gpio_drive,
        .sense = nv50_gpio_sense,
        .reset = nv50_gpio_reset,
-}.base;
+};
+
+int
+g94_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio)
+{
+       return nvkm_gpio_new_(&g94_gpio, device, index, pgpio);
+}