These changes are the raw update to linux-4.4.6-rt14. Kernel sources
[kvmfornfv.git] / kernel / drivers / gpu / drm / nouveau / nvkm / engine / cipher / g84.c
index 13f3042..bfd0162 100644 (file)
 #include <engine/fifo.h>
 
 #include <core/client.h>
-#include <core/engctx.h>
 #include <core/enum.h>
+#include <core/gpuobj.h>
 
-struct g84_cipher_priv {
-       struct nvkm_engine base;
-};
-
-/*******************************************************************************
- * Crypt object classes
- ******************************************************************************/
+#include <nvif/class.h>
 
 static int
-g84_cipher_object_ctor(struct nvkm_object *parent,
-                      struct nvkm_object *engine,
-                      struct nvkm_oclass *oclass, void *data, u32 size,
-                      struct nvkm_object **pobject)
+g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
+                      int align, struct nvkm_gpuobj **pgpuobj)
 {
-       struct nvkm_gpuobj *obj;
-       int ret;
-
-       ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
-                                16, 16, 0, &obj);
-       *pobject = nv_object(obj);
-       if (ret)
-               return ret;
-
-       nv_wo32(obj, 0x00, nv_mclass(obj));
-       nv_wo32(obj, 0x04, 0x00000000);
-       nv_wo32(obj, 0x08, 0x00000000);
-       nv_wo32(obj, 0x0c, 0x00000000);
-       return 0;
+       int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
+                                 align, false, parent, pgpuobj);
+       if (ret == 0) {
+               nvkm_kmap(*pgpuobj);
+               nvkm_wo32(*pgpuobj, 0x00, object->oclass);
+               nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
+               nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
+               nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
+               nvkm_done(*pgpuobj);
+       }
+       return ret;
 }
 
-static struct nvkm_ofuncs
-g84_cipher_ofuncs = {
-       .ctor = g84_cipher_object_ctor,
-       .dtor = _nvkm_gpuobj_dtor,
-       .init = _nvkm_gpuobj_init,
-       .fini = _nvkm_gpuobj_fini,
-       .rd32 = _nvkm_gpuobj_rd32,
-       .wr32 = _nvkm_gpuobj_wr32,
+static const struct nvkm_object_func
+g84_cipher_oclass_func = {
+       .bind = g84_cipher_oclass_bind,
 };
 
-static struct nvkm_oclass
-g84_cipher_sclass[] = {
-       { 0x74c1, &g84_cipher_ofuncs },
-       {}
-};
+static int
+g84_cipher_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
+                      int align, struct nvkm_gpuobj **pgpuobj)
+{
+       return nvkm_gpuobj_new(object->engine->subdev.device, 256,
+                              align, true, parent, pgpuobj);
 
-/*******************************************************************************
- * PCIPHER context
- ******************************************************************************/
+}
 
-static struct nvkm_oclass
+static const struct nvkm_object_func
 g84_cipher_cclass = {
-       .handle = NV_ENGCTX(CIPHER, 0x84),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = _nvkm_engctx_ctor,
-               .dtor = _nvkm_engctx_dtor,
-               .init = _nvkm_engctx_init,
-               .fini = _nvkm_engctx_fini,
-               .rd32 = _nvkm_engctx_rd32,
-               .wr32 = _nvkm_engctx_wr32,
-       },
+       .bind = g84_cipher_cclass_bind,
 };
 
-/*******************************************************************************
- * PCIPHER engine/subdev functions
- ******************************************************************************/
-
 static const struct nvkm_bitfield
 g84_cipher_intr_mask[] = {
        { 0x00000001, "INVALID_STATE" },
@@ -106,79 +77,59 @@ g84_cipher_intr_mask[] = {
 };
 
 static void
-g84_cipher_intr(struct nvkm_subdev *subdev)
+g84_cipher_intr(struct nvkm_engine *cipher)
 {
-       struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
-       struct nvkm_engine *engine = nv_engine(subdev);
-       struct nvkm_object *engctx;
-       struct g84_cipher_priv *priv = (void *)subdev;
-       u32 stat = nv_rd32(priv, 0x102130);
-       u32 mthd = nv_rd32(priv, 0x102190);
-       u32 data = nv_rd32(priv, 0x102194);
-       u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff;
-       int chid;
-
-       engctx = nvkm_engctx_get(engine, inst);
-       chid   = pfifo->chid(pfifo, engctx);
-
+       struct nvkm_subdev *subdev = &cipher->subdev;
+       struct nvkm_device *device = subdev->device;
+       struct nvkm_fifo *fifo = device->fifo;
+       struct nvkm_fifo_chan *chan;
+       u32 stat = nvkm_rd32(device, 0x102130);
+       u32 mthd = nvkm_rd32(device, 0x102190);
+       u32 data = nvkm_rd32(device, 0x102194);
+       u32 inst = nvkm_rd32(device, 0x102188) & 0x7fffffff;
+       unsigned long flags;
+       char msg[128];
+
+       chan = nvkm_fifo_chan_inst(fifo, (u64)inst << 12, &flags);
        if (stat) {
-               nv_error(priv, "%s", "");
-               nvkm_bitfield_print(g84_cipher_intr_mask, stat);
-               pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
-                      chid, (u64)inst << 12, nvkm_client_name(engctx),
-                      mthd, data);
+               nvkm_snprintbf(msg, sizeof(msg), g84_cipher_intr_mask, stat);
+               nvkm_error(subdev,  "%08x [%s] ch %d [%010llx %s] "
+                                   "mthd %04x data %08x\n", stat, msg,
+                          chan ? chan->chid : -1, (u64)inst << 12,
+                          chan ? chan->object.client->name : "unknown",
+                          mthd, data);
        }
+       nvkm_fifo_chan_put(fifo, flags, &chan);
 
-       nv_wr32(priv, 0x102130, stat);
-       nv_wr32(priv, 0x10200c, 0x10);
-
-       nvkm_engctx_put(engctx);
+       nvkm_wr32(device, 0x102130, stat);
+       nvkm_wr32(device, 0x10200c, 0x10);
 }
 
 static int
-g84_cipher_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-               struct nvkm_oclass *oclass, void *data, u32 size,
-               struct nvkm_object **pobject)
+g84_cipher_init(struct nvkm_engine *cipher)
 {
-       struct g84_cipher_priv *priv;
-       int ret;
-
-       ret = nvkm_engine_create(parent, engine, oclass, true,
-                                "PCIPHER", "cipher", &priv);
-       *pobject = nv_object(priv);
-       if (ret)
-               return ret;
-
-       nv_subdev(priv)->unit = 0x00004000;
-       nv_subdev(priv)->intr = g84_cipher_intr;
-       nv_engine(priv)->cclass = &g84_cipher_cclass;
-       nv_engine(priv)->sclass = g84_cipher_sclass;
+       struct nvkm_device *device = cipher->subdev.device;
+       nvkm_wr32(device, 0x102130, 0xffffffff);
+       nvkm_wr32(device, 0x102140, 0xffffffbf);
+       nvkm_wr32(device, 0x10200c, 0x00000010);
        return 0;
 }
 
-static int
-g84_cipher_init(struct nvkm_object *object)
-{
-       struct g84_cipher_priv *priv = (void *)object;
-       int ret;
-
-       ret = nvkm_engine_init(&priv->base);
-       if (ret)
-               return ret;
+static const struct nvkm_engine_func
+g84_cipher = {
+       .init = g84_cipher_init,
+       .intr = g84_cipher_intr,
+       .cclass = &g84_cipher_cclass,
+       .sclass = {
+               { -1, -1, NV74_CIPHER, &g84_cipher_oclass_func },
+               {}
+       }
+};
 
-       nv_wr32(priv, 0x102130, 0xffffffff);
-       nv_wr32(priv, 0x102140, 0xffffffbf);
-       nv_wr32(priv, 0x10200c, 0x00000010);
-       return 0;
+int
+g84_cipher_new(struct nvkm_device *device, int index,
+              struct nvkm_engine **pengine)
+{
+       return nvkm_engine_new_(&g84_cipher, device, index,
+                               0x00004000, true, pengine);
 }
-
-struct nvkm_oclass
-g84_cipher_oclass = {
-       .handle = NV_ENGINE(CIPHER, 0x84),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = g84_cipher_ctor,
-               .dtor = _nvkm_engine_dtor,
-               .init = g84_cipher_init,
-               .fini = _nvkm_engine_fini,
-       },
-};