These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / gpu / drm / nouveau / nouveau_dma.c

diff --git a/kernel/drivers/gpu/drm/nouveau/nouveau_dma.c b/kernel/drivers/gpu/drm/nouveau/nouveau_dma.c
index 6d9245a..d168c63 100644 (file)
--- a/kernel/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/kernel/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -52,9 +52,9 @@ READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout)
 {
        uint64_t val;
 
-       val = nvif_rd32(chan, chan->user_get);
+       val = nvif_rd32(&chan->user, chan->user_get);
         if (chan->user_get_hi)
-                val |= (uint64_t)nvif_rd32(chan, chan->user_get_hi) << 32;
+                val |= (uint64_t)nvif_rd32(&chan->user, chan->user_get_hi) << 32;
 
        /* reset counter as long as GET is still advancing, this is
         * to avoid misdetecting a GPU lockup if the GPU happens to
@@ -82,7 +82,7 @@ void
 nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
              int delta, int length)
 {
-       struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base);
+       struct nouveau_cli *cli = (void *)chan->user.client;
        struct nouveau_bo *pb = chan->push.buffer;
        struct nvkm_vma *vma;
        int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
@@ -103,7 +103,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
        /* Flush writes. */
        nouveau_bo_rd32(pb, 0);
 
-       nvif_wr32(chan, 0x8c, chan->dma.ib_put);
+       nvif_wr32(&chan->user, 0x8c, chan->dma.ib_put);
        chan->dma.ib_free--;
 }
 
@@ -113,7 +113,7 @@ nv50_dma_push_wait(struct nouveau_channel *chan, int count)
        uint32_t cnt = 0, prev_get = 0;
 
        while (chan->dma.ib_free < count) {
-               uint32_t get = nvif_rd32(chan, 0x88);
+               uint32_t get = nvif_rd32(&chan->user, 0x88);
                if (get != prev_get) {
                        prev_get = get;
                        cnt = 0;