These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_ctl.h

diff --git a/kernel/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h b/kernel/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h
index 7a62000..96148c6 100644 (file)
--- a/kernel/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h
+++ b/kernel/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h
@@ -23,7 +23,7 @@
  */
 struct mdp5_ctl_manager;
 struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
-               void __iomem *mmio_base, const struct mdp5_cfg_hw *hw_cfg);
+               void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd);
 void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctlm);
 void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
 
@@ -32,49 +32,32 @@ void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
  * mdp5_ctl_request(ctlm, ...) returns a ctl (CTL resource) handler,
  * which is then used to call the other mdp5_ctl_*(ctl, ...) functions.
  */
-struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, struct drm_crtc *crtc);
+struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
+
 int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
 
 struct mdp5_interface;
-int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, struct mdp5_interface *intf);
+int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_interface *intf,
+                               int lm);
 int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled);
 
 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable);
-
-/*
- * blend_cfg (LM blender config):
- *
- * The function below allows the caller of mdp5_ctl_blend() to specify how pipes
- * are being blended according to their stage (z-order), through @blend_cfg arg.
- */
-static inline u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
-               enum mdp_mixer_stage_id stage)
-{
-       switch (pipe) {
-       case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage);
-       case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage);
-       case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage);
-       case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage);
-       case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage);
-       case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage);
-       case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage);
-       case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage);
-       case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage);
-       case SSPP_RGB3: return MDP5_CTL_LAYER_REG_RGB3(stage);
-       default:        return 0;
-       }
-}
+int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
 
 /*
  * mdp5_ctl_blend() - Blend multiple layers on a Layer Mixer (LM)
  *
- * @blend_cfg: see LM blender config definition below
+ * @stage: array to contain the pipe num for each stage
+ * @stage_cnt: valid stage number in stage array
+ * @ctl_blend_op_flags: blender operation mode flags
  *
  * Note:
  * CTL registers need to be flushed after calling this function
  * (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
  */
-int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u32 blend_cfg);
+#define MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT      BIT(0)
+int mdp5_ctl_blend(struct mdp5_ctl *ctl, u8 *stage, u32 stage_cnt,
+       u32 ctl_blend_op_flags);
 
 /**
  * mdp_ctl_flush_mask...() - Register FLUSH masks
@@ -88,9 +71,8 @@ u32 mdp_ctl_flush_mask_cursor(int cursor_id);
 u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
 
 /* @flush_mask: see CTL flush masks definitions below */
-int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask);
-
-void mdp5_ctl_release(struct mdp5_ctl *ctl);
+u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask);
+u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);