These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / clk / ti / clk-7xx.c

diff --git a/kernel/drivers/clk/ti/clk-7xx.c b/kernel/drivers/clk/ti/clk-7xx.c
index 5d2217a..a911d7d 100644 (file)
--- a/kernel/drivers/clk/ti/clk-7xx.c
+++ b/kernel/drivers/clk/ti/clk-7xx.c
@@ -16,11 +16,11 @@
 #include <linux/clkdev.h>
 #include <linux/clk/ti.h>
 
-#define DRA7_DPLL_ABE_DEFFREQ                          180633600
+#include "clock.h"
+
 #define DRA7_DPLL_GMAC_DEFFREQ                         1000000000
 #define DRA7_DPLL_USB_DEFFREQ                          960000000
 
-
 static struct ti_dt_clk dra7xx_clks[] = {
        DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
        DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
@@ -305,33 +305,19 @@ static struct ti_dt_clk dra7xx_clks[] = {
        DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
        DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
        DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+       DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
        { .node_name = NULL },
 };
 
 int __init dra7xx_dt_clk_init(void)
 {
        int rc;
-       struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+       struct clk *dpll_ck, *hdcp_ck;
 
        ti_dt_clocks_register(dra7xx_clks);
 
        omap2_clk_disable_autoidle_all();
 
-       abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
-       sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
-       dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
-
-       rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
-       if (!rc)
-               rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
-       if (rc)
-               pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
-       dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
-       rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
-       if (rc)
-               pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
-
        dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
        rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
        if (rc)
@@ -347,5 +333,10 @@ int __init dra7xx_dt_clk_init(void)
        if (rc)
                pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 
+       hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+       rc = clk_prepare_enable(hdcp_ck);
+       if (rc)
+               pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
+
        return rc;
 }