These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / clk / socfpga / clk-gate.c

diff --git a/kernel/drivers/clk/socfpga/clk-gate.c b/kernel/drivers/clk/socfpga/clk-gate.c
index dd3a78c..aa7a6e6 100644 (file)
--- a/kernel/drivers/clk/socfpga/clk-gate.c
+++ b/kernel/drivers/clk/socfpga/clk-gate.c
@@ -15,8 +15,7 @@
  * Based from clk-highbank.c
  *
  */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
+#include <linux/slab.h>
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/mfd/syscon.h>
@@ -32,14 +31,10 @@
 #define SOCFPGA_MMC_CLK                        "sdmmc_clk"
 #define SOCFPGA_GPIO_DB_CLK_OFFSET     0xA8
 
-#define streq(a, b) (strcmp((a), (b)) == 0)
-
 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
 /* SDMMC Group for System Manager defines */
 #define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
-       ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
 
 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 {
@@ -110,7 +105,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
                div = socfpgaclk->fixed_div;
        else if (socfpgaclk->div_reg) {
                val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-               val &= div_mask(socfpgaclk->width);
+               val &= GENMASK(socfpgaclk->width - 1, 0);
                /* Check for GPIO_DB_CLK by its offset */
                if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
                        div = val + 1;
@@ -194,7 +189,6 @@ static void __init __socfpga_gate_init(struct device_node *node,
        const char *parent_name[SOCFPGA_MAX_PARENTS];
        struct clk_init_data init;
        int rc;
-       int i = 0;
 
        socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
        if (WARN_ON(!socfpga_clk))
@@ -224,7 +218,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
                socfpga_clk->shift = div_reg[1];
                socfpga_clk->width = div_reg[2];
        } else {
-               socfpga_clk->div_reg = 0;
+               socfpga_clk->div_reg = NULL;
        }
 
        rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
@@ -238,12 +232,9 @@ static void __init __socfpga_gate_init(struct device_node *node,
        init.name = clk_name;
        init.ops = ops;
        init.flags = 0;
-       while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-                       of_clk_get_parent_name(node, i)) != NULL)
-               i++;
 
+       init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
        init.parent_names = parent_name;
-       init.num_parents = i;
        socfpga_clk->hw.hw.init = &init;
 
        clk = clk_register(NULL, &socfpga_clk->hw.hw);