These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / clk / samsung / clk-exynos5250.c

diff --git a/kernel/drivers/clk/samsung/clk-exynos5250.c b/kernel/drivers/clk/samsung/clk-exynos5250.c
index 70ec3d2..5bebf8c 100644 (file)
--- a/kernel/drivers/clk/samsung/clk-exynos5250.c
+++ b/kernel/drivers/clk/samsung/clk-exynos5250.c
@@ -11,14 +11,13 @@
 */
 
 #include <dt-bindings/clock/exynos5250.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/syscore_ops.h>
 
 #include "clk.h"
+#include "clk-cpu.h"
 
 #define APLL_LOCK              0x0
 #define APLL_CON0              0x100
@@ -223,9 +222,13 @@ PNAME(mout_mpll_user_p)    = { "fin_pll", "mout_mpll" };
 PNAME(mout_bpll_user_p)        = { "fin_pll", "mout_bpll" };
 PNAME(mout_aclk166_p)  = { "mout_cpll", "mout_mpll_user" };
 PNAME(mout_aclk200_p)  = { "mout_mpll_user", "mout_bpll_user" };
+PNAME(mout_aclk300_p)  = { "mout_aclk300_disp1_mid",
+                           "mout_aclk300_disp1_mid1" };
 PNAME(mout_aclk400_p)  = { "mout_aclk400_g3d_mid", "mout_gpll" };
 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
+PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
+PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
 PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
 PNAME(mout_hdmi_p)     = { "div_hdmi_pixel", "sclk_hdmiphy" };
@@ -304,9 +307,13 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
         */
        MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
        MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+       MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
+       MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
        MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
        MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
 
+       MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
+               8, 1),
        MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
        MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
 
@@ -317,7 +324,10 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
        MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
        MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
 
-       MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
+       MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
+               mout_aclk200_sub_p, SRC_TOP3, 4, 1),
+       MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
+               mout_aclk300_sub_p, SRC_TOP3, 6, 1),
        MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
        MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
        MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
@@ -393,6 +403,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
        DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
        DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
                                                        24, 3),
+       DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
 
        DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
        DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
@@ -748,6 +759,32 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
                VPLL_LOCK, VPLL_CON0, NULL),
 };
 
+#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud)         \
+               ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+                ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
+#define E5250_CPU_DIV1(hpm, copy)                                      \
+               (((hpm) << 4) | (copy))
+
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
+       { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+       { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+       { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+       { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+       { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+       { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+       { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+       { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+       {  0 },
+};
+
 static const struct of_device_id ext_clk_match[] __initconst = {
        { .compatible = "samsung,clock-xxti", .data = (void *)0, },
        { },
@@ -797,6 +834,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
                        ARRAY_SIZE(exynos5250_div_clks));
        samsung_clk_register_gate(ctx, exynos5250_gate_clks,
                        ARRAY_SIZE(exynos5250_gate_clks));
+       exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+                       mout_cpu_p[0], mout_cpu_p[1], 0x200,
+                       exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
+                       CLK_CPU_HAS_DIV1);
 
        /*
         * Enable arm clock down (in idle) and set arm divider