These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / clk / qcom / mmcc-apq8084.c

diff --git a/kernel/drivers/clk/qcom/mmcc-apq8084.c b/kernel/drivers/clk/qcom/mmcc-apq8084.c
index 1b17df2..30777f9 100644 (file)
--- a/kernel/drivers/clk/qcom/mmcc-apq8084.c
+++ b/kernel/drivers/clk/qcom/mmcc-apq8084.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -26,6 +26,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 enum {
        P_XO,
@@ -53,7 +54,7 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
        { P_GPLL0, 5 }
 };
 
-static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
+static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
        "xo",
        "mmpll0_vote",
        "mmpll1_vote",
@@ -69,7 +70,7 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
        { P_DSI1PLL, 3 }
 };
 
-static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
+static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
        "xo",
        "mmpll0_vote",
        "hdmipll",
@@ -86,7 +87,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
        { P_MMPLL2, 3 }
 };
 
-static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
+static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
        "xo",
        "mmpll0_vote",
        "mmpll1_vote",
@@ -102,7 +103,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
        { P_MMPLL3, 3 }
 };
 
-static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
+static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
        "xo",
        "mmpll0_vote",
        "mmpll1_vote",
@@ -119,7 +120,7 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
        { P_DSI1PLL, 2 }
 };
 
-static const char *mmcc_xo_dsi_hdmi_edp[] = {
+static const char * const mmcc_xo_dsi_hdmi_edp[] = {
        "xo",
        "edp_link_clk",
        "hdmipll",
@@ -137,7 +138,7 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
        { P_DSI1PLL, 2 }
 };
 
-static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
+static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
        "xo",
        "edp_link_clk",
        "hdmipll",
@@ -155,7 +156,7 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
        { P_DSI1PLL_BYTE, 2 }
 };
 
-static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
+static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
        "xo",
        "edp_link_clk",
        "hdmipll",
@@ -172,7 +173,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
        { P_MMPLL4, 3 }
 };
 
-static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
+static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
        "xo",
        "mmpll0",
        "mmpll1",
@@ -189,7 +190,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
        { P_GPLL1, 4 }
 };
 
-static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
+static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
        "xo",
        "mmpll0",
        "mmpll1",
@@ -208,7 +209,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
        { P_MMSLEEP, 6 }
 };
 
-static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
+static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
        "xo",
        "mmpll0",
        "mmpll1",
@@ -571,17 +572,11 @@ static struct clk_rcg2 jpeg2_clk_src = {
        },
 };
 
-static struct freq_tbl pixel_freq_tbl[] = {
-       { .src = P_DSI0PLL },
-       { }
-};
-
 static struct clk_rcg2 pclk0_clk_src = {
        .cmd_rcgr = 0x2000,
        .mnd_width = 8,
        .hid_width = 5,
        .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
-       .freq_tbl = pixel_freq_tbl,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "pclk0_clk_src",
                .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
@@ -596,7 +591,6 @@ static struct clk_rcg2 pclk1_clk_src = {
        .mnd_width = 8,
        .hid_width = 5,
        .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
-       .freq_tbl = pixel_freq_tbl,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "pclk1_clk_src",
                .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
@@ -844,21 +838,15 @@ static struct clk_rcg2 cpp_clk_src = {
        },
 };
 
-static struct freq_tbl byte_freq_tbl[] = {
-       { .src = P_DSI0PLL_BYTE },
-       { }
-};
-
 static struct clk_rcg2 byte0_clk_src = {
        .cmd_rcgr = 0x2120,
        .hid_width = 5,
        .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
-       .freq_tbl = byte_freq_tbl,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "byte0_clk_src",
                .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
                .num_parents = 6,
-               .ops = &clk_byte_ops,
+               .ops = &clk_byte2_ops,
                .flags = CLK_SET_RATE_PARENT,
        },
 };
@@ -867,12 +855,11 @@ static struct clk_rcg2 byte1_clk_src = {
        .cmd_rcgr = 0x2140,
        .hid_width = 5,
        .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
-       .freq_tbl = byte_freq_tbl,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "byte1_clk_src",
                .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
                .num_parents = 6,
-               .ops = &clk_byte_ops,
+               .ops = &clk_byte2_ops,
                .flags = CLK_SET_RATE_PARENT,
        },
 };
@@ -3077,6 +3064,76 @@ static const struct pll_config mmpll3_config = {
        .aux_output_mask = BIT(1),
 };
 
+static struct gdsc venus0_gdsc = {
+       .gdscr = 0x1024,
+       .pd = {
+               .name = "venus0",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc venus0_core0_gdsc = {
+       .gdscr = 0x1040,
+       .pd = {
+               .name = "venus0_core0",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc venus0_core1_gdsc = {
+       .gdscr = 0x1044,
+       .pd = {
+               .name = "venus0_core1",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc mdss_gdsc = {
+       .gdscr = 0x2304,
+       .cxcs = (unsigned int []){ 0x231c, 0x2320 },
+       .cxc_count = 2,
+       .pd = {
+               .name = "mdss",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+       .gdscr = 0x35a4,
+       .pd = {
+               .name = "camss_jpeg",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_vfe_gdsc = {
+       .gdscr = 0x36a4,
+       .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
+       .cxc_count = 3,
+       .pd = {
+               .name = "camss_vfe",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+       .gdscr = 0x4024,
+       .cxcs = (unsigned int []){ 0x4028 },
+       .cxc_count = 1,
+       .pd = {
+               .name = "oxili",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxilicx_gdsc = {
+       .gdscr = 0x4034,
+       .pd = {
+               .name = "oxilicx",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+};
+
 static struct clk_regmap *mmcc_apq8084_clocks[] = {
        [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
        [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -3294,6 +3351,17 @@ static const struct qcom_reset_map mmcc_apq8084_resets[] = {
        [MMSSNOCAXI_RESET] = { 0x5060 },
 };
 
+static struct gdsc *mmcc_apq8084_gdscs[] = {
+       [VENUS0_GDSC] = &venus0_gdsc,
+       [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
+       [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
+       [MDSS_GDSC] = &mdss_gdsc,
+       [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
+       [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
+       [OXILI_GDSC] = &oxili_gdsc,
+       [OXILICX_GDSC] = &oxilicx_gdsc,
+};
+
 static const struct regmap_config mmcc_apq8084_regmap_config = {
        .reg_bits       = 32,
        .reg_stride     = 4,
@@ -3308,6 +3376,8 @@ static const struct qcom_cc_desc mmcc_apq8084_desc = {
        .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
        .resets = mmcc_apq8084_resets,
        .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
+       .gdscs = mmcc_apq8084_gdscs,
+       .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
 };
 
 static const struct of_device_id mmcc_apq8084_match_table[] = {
@@ -3332,15 +3402,8 @@ static int mmcc_apq8084_probe(struct platform_device *pdev)
        return 0;
 }
 
-static int mmcc_apq8084_remove(struct platform_device *pdev)
-{
-       qcom_cc_remove(pdev);
-       return 0;
-}
-
 static struct platform_driver mmcc_apq8084_driver = {
        .probe          = mmcc_apq8084_probe,
-       .remove         = mmcc_apq8084_remove,
        .driver         = {
                .name   = "mmcc-apq8084",
                .of_match_table = mmcc_apq8084_match_table,