These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / clk / clk-xgene.c

diff --git a/kernel/drivers/clk/clk-xgene.c b/kernel/drivers/clk/clk-xgene.c
index dd8a62d..27c0da2 100644 (file)
--- a/kernel/drivers/clk/clk-xgene.c
+++ b/kernel/drivers/clk/clk-xgene.c
@@ -27,7 +27,6 @@
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
 #include <linux/of_address.h>
-#include <asm/setup.h>
 
 /* Register SCU_PCPPLL bit fields */
 #define N_DIV_RD(src)                  (((src) & 0x000001ff))
@@ -42,12 +41,12 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
-static inline u32 xgene_clk_read(void *csr)
+static inline u32 xgene_clk_read(void __iomem *csr)
 {
        return readl_relaxed(csr);
 }
 
-static inline void xgene_clk_write(u32 data, void *csr)
+static inline void xgene_clk_write(u32 data, void __iomem *csr)
 {
        return writel_relaxed(data, csr);
 }
@@ -60,7 +59,6 @@ enum xgene_pll_type {
 
 struct xgene_clk_pll {
        struct clk_hw   hw;
-       const char      *name;
        void __iomem    *reg;
        spinlock_t      *lock;
        u32             pll_offset;
@@ -75,7 +73,7 @@ static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
        u32 data;
 
        data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
-       pr_debug("%s pll %s\n", pllclk->name,
+       pr_debug("%s pll %s\n", clk_hw_get_name(hw),
                data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");
 
        return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
@@ -113,13 +111,13 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
                fref = parent_rate / nref;
                fvco = fref * nfb;
        }
-       pr_debug("%s pll recalc rate %ld parent %ld\n", pllclk->name,
+       pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
                fvco / nout, parent_rate);
 
        return fvco / nout;
 }
 
-const struct clk_ops xgene_clk_pll_ops = {
+static const struct clk_ops xgene_clk_pll_ops = {
        .is_enabled = xgene_clk_pll_is_enabled,
        .recalc_rate = xgene_clk_pll_recalc_rate,
 };
@@ -146,7 +144,6 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
        init.parent_names = parent_name ? &parent_name : NULL;
        init.num_parents = parent_name ? 1 : 0;
 
-       apmclk->name = name;
        apmclk->reg = reg;
        apmclk->lock = lock;
        apmclk->pll_offset = pll_offset;
@@ -167,7 +164,7 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty
 {
         const char *clk_name = np->full_name;
         struct clk *clk;
-        void *reg;
+        void __iomem *reg;
 
         reg = of_iomap(np, 0);
         if (reg == NULL) {
@@ -210,7 +207,6 @@ struct xgene_dev_parameters {
 
 struct xgene_clk {
        struct clk_hw   hw;
-       const char      *name;
        spinlock_t      *lock;
        struct xgene_dev_parameters     param;
 };
@@ -222,20 +218,22 @@ static int xgene_clk_enable(struct clk_hw *hw)
        struct xgene_clk *pclk = to_xgene_clk(hw);
        unsigned long flags = 0;
        u32 data;
+       phys_addr_t reg;
 
        if (pclk->lock)
                spin_lock_irqsave(pclk->lock, flags);
 
        if (pclk->param.csr_reg != NULL) {
-               pr_debug("%s clock enabled\n", pclk->name);
+               pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
+               reg = __pa(pclk->param.csr_reg);
                /* First enable the clock */
                data = xgene_clk_read(pclk->param.csr_reg +
                                        pclk->param.reg_clk_offset);
                data |= pclk->param.reg_clk_mask;
                xgene_clk_write(data, pclk->param.csr_reg +
                                        pclk->param.reg_clk_offset);
-               pr_debug("%s clock PADDR base 0x%016LX clk offset 0x%08X mask 0x%08X value 0x%08X\n",
-                       pclk->name, __pa(pclk->param.csr_reg),
+               pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
+                       clk_hw_get_name(hw), &reg,
                        pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
                        data);
 
@@ -245,8 +243,8 @@ static int xgene_clk_enable(struct clk_hw *hw)
                data &= ~pclk->param.reg_csr_mask;
                xgene_clk_write(data, pclk->param.csr_reg +
                                        pclk->param.reg_csr_offset);
-               pr_debug("%s CSR RESET PADDR base 0x%016LX csr offset 0x%08X mask 0x%08X value 0x%08X\n",
-                       pclk->name, __pa(pclk->param.csr_reg),
+               pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
+                       clk_hw_get_name(hw), &reg,
                        pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
                        data);
        }
@@ -267,7 +265,7 @@ static void xgene_clk_disable(struct clk_hw *hw)
                spin_lock_irqsave(pclk->lock, flags);
 
        if (pclk->param.csr_reg != NULL) {
-               pr_debug("%s clock disabled\n", pclk->name);
+               pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
                /* First put the CSR in reset */
                data = xgene_clk_read(pclk->param.csr_reg +
                                        pclk->param.reg_csr_offset);
@@ -293,10 +291,10 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
        u32 data = 0;
 
        if (pclk->param.csr_reg != NULL) {
-               pr_debug("%s clock checking\n", pclk->name);
+               pr_debug("%s clock checking\n", clk_hw_get_name(hw));
                data = xgene_clk_read(pclk->param.csr_reg +
                                        pclk->param.reg_clk_offset);
-               pr_debug("%s clock is %s\n", pclk->name,
+               pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
                        data & pclk->param.reg_clk_mask ? "enabled" :
                                                        "disabled");
        }
@@ -319,11 +317,13 @@ static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
                data &= (1 << pclk->param.reg_divider_width) - 1;
 
                pr_debug("%s clock recalc rate %ld parent %ld\n",
-                       pclk->name, parent_rate / data, parent_rate);
+                       clk_hw_get_name(hw),
+                       parent_rate / data, parent_rate);
+
                return parent_rate / data;
        } else {
                pr_debug("%s clock recalc rate %ld parent %ld\n",
-                       pclk->name, parent_rate, parent_rate);
+                       clk_hw_get_name(hw), parent_rate, parent_rate);
                return parent_rate;
        }
 }
@@ -355,7 +355,7 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
                data |= divider;
                xgene_clk_write(data, pclk->param.divider_reg +
                                        pclk->param.reg_divider_offset);
-               pr_debug("%s clock set rate %ld\n", pclk->name,
+               pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
                        parent_rate / divider_save);
        } else {
                divider_save = 1;
@@ -386,7 +386,7 @@ static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
        return parent_rate / divider;
 }
 
-const struct clk_ops xgene_clk_ops = {
+static const struct clk_ops xgene_clk_ops = {
        .enable = xgene_clk_enable,
        .disable = xgene_clk_disable,
        .is_enabled = xgene_clk_is_enabled,
@@ -417,7 +417,6 @@ static struct clk *xgene_register_clk(struct device *dev,
        init.parent_names = parent_name ? &parent_name : NULL;
        init.num_parents = parent_name ? 1 : 0;
 
-       apmclk->name = name;
        apmclk->lock = lock;
        apmclk->hw.init = &init;
        apmclk->param = *parameters;
@@ -456,7 +455,7 @@ static void __init xgene_devclk_init(struct device_node *np)
        parameters.csr_reg = NULL;
        parameters.divider_reg = NULL;
        for (i = 0; i < 2; i++) {
-               void *map_res;
+               void __iomem *map_res;
                rc = of_address_to_resource(np, i, &res);
                if (rc != 0) {
                        if (i == 0) {