These changes are the raw update to linux-4.4.6-rt14. Kernel sources
[kvmfornfv.git] / kernel / arch / powerpc / platforms / powernv / setup.c
index 16fdcb2..a9a8fa3 100644 (file)
 #include <asm/opal.h>
 #include <asm/kexec.h>
 #include <asm/smp.h>
-#include <asm/cputhreads.h>
-#include <asm/cpuidle.h>
-#include <asm/code-patching.h>
 
 #include "powernv.h"
-#include "subcore.h"
 
 static void __init pnv_setup_arch(void)
 {
@@ -111,7 +107,7 @@ static void pnv_prepare_going_down(void)
         * Disable all notifiers from OPAL, we can't
         * service interrupts anymore anyway
         */
-       opal_notifier_disable();
+       opal_event_shutdown();
 
        /* Soft disable interrupts */
        local_irq_disable();
@@ -169,21 +165,6 @@ static void pnv_progress(char *s, unsigned short hex)
 {
 }
 
-static int pnv_dma_set_mask(struct device *dev, u64 dma_mask)
-{
-       if (dev_is_pci(dev))
-               return pnv_pci_dma_set_mask(to_pci_dev(dev), dma_mask);
-       return __dma_set_mask(dev, dma_mask);
-}
-
-static u64 pnv_dma_get_required_mask(struct device *dev)
-{
-       if (dev_is_pci(dev))
-               return pnv_pci_dma_get_required_mask(to_pci_dev(dev));
-
-       return __dma_get_required_mask(dev);
-}
-
 static void pnv_shutdown(void)
 {
        /* Let the PCI code clear up IODA tables */
@@ -206,7 +187,7 @@ static void pnv_kexec_wait_secondaries_down(void)
 
        for_each_online_cpu(i) {
                uint8_t status;
-               int64_t rc;
+               int64_t rc, timeout = 1000;
 
                if (i == my_cpu)
                        continue;
@@ -223,6 +204,18 @@ static void pnv_kexec_wait_secondaries_down(void)
                                       i, paca[i].hw_cpu_id);
                                notified = i;
                        }
+
+                       /*
+                        * On crash secondaries might be unreachable or hung,
+                        * so timeout if we've waited too long
+                        * */
+                       mdelay(1);
+                       if (timeout-- == 0) {
+                               printk(KERN_ERR "kexec: timed out waiting for "
+                                      "cpu %d (physical %d) to enter OPAL\n",
+                                      i, paca[i].hw_cpu_id);
+                               break;
+                       }
                }
        }
 }
@@ -244,16 +237,16 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
 
                /* Return the CPU to OPAL */
                opal_return_cpu();
-       } else if (crash_shutdown) {
-               /*
-                * On crash, we don't wait for secondaries to go
-                * down as they might be unreachable or hung, so
-                * instead we just wait a bit and move on.
-                */
-               mdelay(1);
        } else {
                /* Primary waits for the secondaries to have reached OPAL */
                pnv_kexec_wait_secondaries_down();
+
+               /*
+                * We might be running as little-endian - now that interrupts
+                * are disabled, reset the HILE bit to big-endian so we don't
+                * take interrupts in the wrong endian later
+                */
+               opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_BE);
        }
 }
 #endif /* CONFIG_KEXEC */
@@ -277,173 +270,6 @@ static void __init pnv_setup_machdep_opal(void)
        ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
 }
 
-static u32 supported_cpuidle_states;
-
-int pnv_save_sprs_for_winkle(void)
-{
-       int cpu;
-       int rc;
-
-       /*
-        * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric accross
-        * all cpus at boot. Get these reg values of current cpu and use the
-        * same accross all cpus.
-        */
-       uint64_t lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1;
-       uint64_t hid0_val = mfspr(SPRN_HID0);
-       uint64_t hid1_val = mfspr(SPRN_HID1);
-       uint64_t hid4_val = mfspr(SPRN_HID4);
-       uint64_t hid5_val = mfspr(SPRN_HID5);
-       uint64_t hmeer_val = mfspr(SPRN_HMEER);
-
-       for_each_possible_cpu(cpu) {
-               uint64_t pir = get_hard_smp_processor_id(cpu);
-               uint64_t hsprg0_val = (uint64_t)&paca[cpu];
-
-               /*
-                * HSPRG0 is used to store the cpu's pointer to paca. Hence last
-                * 3 bits are guaranteed to be 0. Program slw to restore HSPRG0
-                * with 63rd bit set, so that when a thread wakes up at 0x100 we
-                * can use this bit to distinguish between fastsleep and
-                * deep winkle.
-                */
-               hsprg0_val |= 1;
-
-               rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val);
-               if (rc != 0)
-                       return rc;
-
-               rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);
-               if (rc != 0)
-                       return rc;
-
-               /* HIDs are per core registers */
-               if (cpu_thread_in_core(cpu) == 0) {
-
-                       rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val);
-                       if (rc != 0)
-                               return rc;
-
-                       rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val);
-                       if (rc != 0)
-                               return rc;
-
-                       rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val);
-                       if (rc != 0)
-                               return rc;
-
-                       rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val);
-                       if (rc != 0)
-                               return rc;
-
-                       rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val);
-                       if (rc != 0)
-                               return rc;
-               }
-       }
-
-       return 0;
-}
-
-static void pnv_alloc_idle_core_states(void)
-{
-       int i, j;
-       int nr_cores = cpu_nr_cores();
-       u32 *core_idle_state;
-
-       /*
-        * core_idle_state - First 8 bits track the idle state of each thread
-        * of the core. The 8th bit is the lock bit. Initially all thread bits
-        * are set. They are cleared when the thread enters deep idle state
-        * like sleep and winkle. Initially the lock bit is cleared.
-        * The lock bit has 2 purposes
-        * a. While the first thread is restoring core state, it prevents
-        * other threads in the core from switching to process context.
-        * b. While the last thread in the core is saving the core state, it
-        * prevents a different thread from waking up.
-        */
-       for (i = 0; i < nr_cores; i++) {
-               int first_cpu = i * threads_per_core;
-               int node = cpu_to_node(first_cpu);
-
-               core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, node);
-               *core_idle_state = PNV_CORE_IDLE_THREAD_BITS;
-
-               for (j = 0; j < threads_per_core; j++) {
-                       int cpu = first_cpu + j;
-
-                       paca[cpu].core_idle_state_ptr = core_idle_state;
-                       paca[cpu].thread_idle_state = PNV_THREAD_RUNNING;
-                       paca[cpu].thread_mask = 1 << j;
-               }
-       }
-
-       update_subcore_sibling_mask();
-
-       if (supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED)
-               pnv_save_sprs_for_winkle();
-}
-
-u32 pnv_get_supported_cpuidle_states(void)
-{
-       return supported_cpuidle_states;
-}
-EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states);
-
-static int __init pnv_init_idle_states(void)
-{
-       struct device_node *power_mgt;
-       int dt_idle_states;
-       u32 *flags;
-       int i;
-
-       supported_cpuidle_states = 0;
-
-       if (cpuidle_disable != IDLE_NO_OVERRIDE)
-               goto out;
-
-       if (!firmware_has_feature(FW_FEATURE_OPALv3))
-               goto out;
-
-       power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
-       if (!power_mgt) {
-               pr_warn("opal: PowerMgmt Node not found\n");
-               goto out;
-       }
-       dt_idle_states = of_property_count_u32_elems(power_mgt,
-                       "ibm,cpu-idle-state-flags");
-       if (dt_idle_states < 0) {
-               pr_warn("cpuidle-powernv: no idle states found in the DT\n");
-               goto out;
-       }
-
-       flags = kzalloc(sizeof(*flags) * dt_idle_states, GFP_KERNEL);
-       if (of_property_read_u32_array(power_mgt,
-                       "ibm,cpu-idle-state-flags", flags, dt_idle_states)) {
-               pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n");
-               goto out_free;
-       }
-
-       for (i = 0; i < dt_idle_states; i++)
-               supported_cpuidle_states |= flags[i];
-
-       if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
-               patch_instruction(
-                       (unsigned int *)pnv_fastsleep_workaround_at_entry,
-                       PPC_INST_NOP);
-               patch_instruction(
-                       (unsigned int *)pnv_fastsleep_workaround_at_exit,
-                       PPC_INST_NOP);
-       }
-       pnv_alloc_idle_core_states();
-out_free:
-       kfree(flags);
-out:
-       return 0;
-}
-
-subsys_initcall(pnv_init_idle_states);
-
 static int __init pnv_probe(void)
 {
        unsigned long root = of_get_flat_dt_root();
@@ -492,8 +318,6 @@ define_machine(powernv) {
        .machine_shutdown       = pnv_shutdown,
        .power_save             = power7_idle,
        .calibrate_decr         = generic_calibrate_decr,
-       .dma_set_mask           = pnv_dma_set_mask,
-       .dma_get_required_mask  = pnv_dma_get_required_mask,
 #ifdef CONFIG_KEXEC
        .kexec_cpu_down         = pnv_kexec_cpu_down,
 #endif