These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / arch / powerpc / mm / tlb_nohash.c

diff --git a/kernel/arch/powerpc/mm/tlb_nohash.c b/kernel/arch/powerpc/mm/tlb_nohash.c
index cbd3d06..bb04e4d 100644 (file)
--- a/kernel/arch/powerpc/mm/tlb_nohash.c
+++ b/kernel/arch/powerpc/mm/tlb_nohash.c
@@ -42,6 +42,7 @@
 #include <asm/tlbflush.h>
 #include <asm/tlb.h>
 #include <asm/code-patching.h>
+#include <asm/cputhreads.h>
 #include <asm/hugetlb.h>
 #include <asm/paca.h>
 
@@ -217,7 +218,7 @@ static DEFINE_RAW_SPINLOCK(tlbivax_lock);
 static int mm_is_core_local(struct mm_struct *mm)
 {
        return cpumask_subset(mm_cpumask(mm),
-                             topology_thread_cpumask(smp_processor_id()));
+                             topology_sibling_cpumask(smp_processor_id()));
 }
 
 struct tlb_flush_param {
@@ -628,10 +629,26 @@ static void early_init_this_mmu(void)
 #ifdef CONFIG_PPC_FSL_BOOK3E
        if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
                unsigned int num_cams;
+               int __maybe_unused cpu = smp_processor_id();
+               bool map = true;
 
                /* use a quarter of the TLBCAM for bolted linear map */
                num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
-               linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
+
+               /*
+                * Only do the mapping once per core, or else the
+                * transient mapping would cause problems.
+                */
+#ifdef CONFIG_SMP
+               if (cpu != boot_cpuid &&
+                   (cpu != cpu_first_thread_sibling(cpu) ||
+                    cpu == cpu_first_thread_sibling(boot_cpuid)))
+                       map = false;
+#endif
+
+               if (map)
+                       linear_map_top = map_mem_in_cams(linear_map_top,
+                                                        num_cams, false);
        }
 #endif
 
@@ -729,10 +746,14 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
         * entries are supported though that may eventually
         * change.
         *
-        * on FSL Embedded 64-bit, we adjust the RMA size to match the
-        * first bolted TLB entry size.  We still limit max to 1G even if
-        * the TLB could cover more.  This is due to what the early init
-        * code is setup to do.
+        * on FSL Embedded 64-bit, usually all RAM is bolted, but with
+        * unusual memory sizes it's possible for some RAM to not be mapped
+        * (such RAM is not used at all by Linux, since we don't support
+        * highmem on 64-bit).  We limit ppc64_rma_size to what would be
+        * mappable if this memblock is the only one.  Additional memblocks
+        * can only increase, not decrease, the amount that ends up getting
+        * mapped.  We still limit max to 1G even if we'll eventually map
+        * more.  This is due to what the early init code is set up to do.
         *
         * We crop it to the size of the first MEMBLOCK to
         * avoid going over total available memory just in case...
@@ -740,8 +761,14 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 #ifdef CONFIG_PPC_FSL_BOOK3E
        if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
                unsigned long linear_sz;
-               linear_sz = calc_cam_sz(first_memblock_size, PAGE_OFFSET,
-                                       first_memblock_base);
+               unsigned int num_cams;
+
+               /* use a quarter of the TLBCAM for bolted linear map */
+               num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
+
+               linear_sz = map_mem_in_cams(first_memblock_size, num_cams,
+                                           true);
+
                ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
        } else
 #endif