These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / arch / mips / ralink / mt7620.c

diff --git a/kernel/arch/mips/ralink/mt7620.c b/kernel/arch/mips/ralink/mt7620.c
index 2ea5ff6..dfb04fc 100644 (file)
--- a/kernel/arch/mips/ralink/mt7620.c
+++ b/kernel/arch/mips/ralink/mt7620.c
@@ -37,8 +37,17 @@
 #define PMU1_CFG               0x8C
 #define DIG_SW_SEL             BIT(25)
 
-/* is this a MT7620 or a MT7628 */
-enum mt762x_soc_type mt762x_soc;
+/* clock scaling */
+#define CLKCFG_FDIV_MASK       0x1f00
+#define CLKCFG_FDIV_USB_VAL    0x0300
+#define CLKCFG_FFRAC_MASK      0x001f
+#define CLKCFG_FFRAC_USB_VAL   0x0003
+
+/* EFUSE bits */
+#define EFUSE_MT7688           0x100000
+
+/* DRAM type bit */
+#define DRAM_TYPE_MT7628_MASK  0x1
 
 /* does the board have sdram or ddram */
 static int dram_type;
@@ -227,6 +236,12 @@ static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
        { 0 }
 };
 
+static inline int is_mt76x8(void)
+{
+       return ralink_soc == MT762X_SOC_MT7628AN ||
+              ralink_soc == MT762X_SOC_MT7688;
+}
+
 static __init u32
 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
 {
@@ -381,7 +396,7 @@ void __init ralink_clk_init(void)
 #define RINT(x)                ((x) / 1000000)
 #define RFRAC(x)       (((x) / 1000) % 1000)
 
-       if (mt762x_soc == MT762X_SOC_MT7628AN) {
+       if (is_mt76x8()) {
                if (xtal_rate == MHZ(40))
                        cpu_rate = MHZ(580);
                else
@@ -423,6 +438,20 @@ void __init ralink_clk_init(void)
        ralink_clk_add("10000b00.spi", sys_rate);
        ralink_clk_add("10000c00.uartlite", periph_rate);
        ralink_clk_add("10180000.wmac", xtal_rate);
+
+       if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
+               /*
+                * When the CPU goes into sleep mode, the BUS clock will be
+                * too low for USB to function properly. Adjust the busses
+                * fractional divider to fix this
+                */
+               u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+
+               val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
+               val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
+
+               rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
+       }
 }
 
 void __init ralink_of_remap(void)
@@ -499,20 +528,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
        if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
                if (bga) {
-                       mt762x_soc = MT762X_SOC_MT7620A;
+                       ralink_soc = MT762X_SOC_MT7620A;
                        name = "MT7620A";
                        soc_info->compatible = "ralink,mt7620a-soc";
                } else {
-                       mt762x_soc = MT762X_SOC_MT7620N;
+                       ralink_soc = MT762X_SOC_MT7620N;
                        name = "MT7620N";
                        soc_info->compatible = "ralink,mt7620n-soc";
-#ifdef CONFIG_PCI
-                       panic("mt7620n is only supported for non pci kernels");
-#endif
                }
        } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
-               mt762x_soc = MT762X_SOC_MT7628AN;
-               name = "MT7628AN";
+               u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
+
+               if (efuse & EFUSE_MT7688) {
+                       ralink_soc = MT762X_SOC_MT7688;
+                       name = "MT7688";
+               } else {
+                       ralink_soc = MT762X_SOC_MT7628AN;
+                       name = "MT7628AN";
+               }
                soc_info->compatible = "ralink,mt7628an-soc";
        } else {
                panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
@@ -525,10 +558,14 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
                (rev & CHIP_REV_ECO_MASK));
 
        cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
-       dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
+       if (is_mt76x8())
+               dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
+       else
+               dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
+                           SYSCFG0_DRAM_TYPE_MASK;
 
        soc_info->mem_base = MT7620_DRAM_BASE;
-       if (mt762x_soc == MT762X_SOC_MT7628AN)
+       if (is_mt76x8())
                mt7628_dram_init(soc_info);
        else
                mt7620_dram_init(soc_info);
@@ -541,7 +578,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
        pr_info("Digital PMU set to %s control\n",
                (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 
-       if (mt762x_soc == MT762X_SOC_MT7628AN)
+       if (is_mt76x8())
                rt2880_pinmux_data = mt7628an_pinmux_data;
        else
                rt2880_pinmux_data = mt7620a_pinmux_data;