These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / arch / mips / include / asm / cpu.h

diff --git a/kernel/arch/mips/include/asm/cpu.h b/kernel/arch/mips/include/asm/cpu.h
index e3adca1..82ad15f 100644 (file)
--- a/kernel/arch/mips/include/asm/cpu.h
+++ b/kernel/arch/mips/include/asm/cpu.h
@@ -42,7 +42,9 @@
 #define PRID_COMP_LEXRA                0x0b0000
 #define PRID_COMP_NETLOGIC     0x0c0000
 #define PRID_COMP_CAVIUM       0x0d0000
-#define PRID_COMP_INGENIC      0xd00000
+#define PRID_COMP_INGENIC_D0   0xd00000        /* JZ4740, JZ4750 */
+#define PRID_COMP_INGENIC_D1   0xd10000        /* JZ4770, JZ4775 */
+#define PRID_COMP_INGENIC_E1   0xe10000        /* JZ4780 */
 
 /*
  * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
@@ -118,6 +120,7 @@
 #define PRID_IMP_PROAPTIV_MP   0xa300
 #define PRID_IMP_M5150         0xa700
 #define PRID_IMP_P5600         0xa800
+#define PRID_IMP_I6400         0xa900
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -168,7 +171,7 @@
 #define PRID_IMP_CAVIUM_CN70XX 0x9600
 
 /*
- * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
  */
 
 #define PRID_IMP_JZRISC               0x0200
@@ -305,6 +308,7 @@ enum cpu_type_enum {
        CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
        CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
+       CPU_I6400,
 
        /*
         * MIPS64 class processors
@@ -379,6 +383,9 @@ enum cpu_type_enum {
 #define MIPS_CPU_RW_LLB                0x1000000000ull /* LLADDR/LLB writes are allowed */
 #define MIPS_CPU_XPA           0x2000000000ull /* CPU supports Extended Physical Addressing */
 #define MIPS_CPU_CDMM          0x4000000000ull /* CPU has Common Device Memory Map */
+#define MIPS_CPU_BP_GHIST      0x8000000000ull /* R12K+ Branch Prediction Global History */
+#define MIPS_CPU_SP            0x10000000000ull /* Small (1KB) page support */
+#define MIPS_CPU_FTLB          0x20000000000ull /* CPU has Fixed-page-size TLB */
 
 /*
  * CPU ASE encodings