These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / arch / arm64 / kernel / alternative.c

diff --git a/kernel/arch/arm64/kernel/alternative.c b/kernel/arch/arm64/kernel/alternative.c
index 28f8365..ab9db0e 100644 (file)
--- a/kernel/arch/arm64/kernel/alternative.c
+++ b/kernel/arch/arm64/kernel/alternative.c
@@ -24,8 +24,13 @@
 #include <asm/cacheflush.h>
 #include <asm/alternative.h>
 #include <asm/cpufeature.h>
+#include <asm/insn.h>
 #include <linux/stop_machine.h>
 
+#define __ALT_PTR(a,f)         (u32 *)((void *)&(a)->f + (a)->f)
+#define ALT_ORIG_PTR(a)                __ALT_PTR(a, orig_offset)
+#define ALT_REPL_PTR(a)                __ALT_PTR(a, alt_offset)
+
 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
 
 struct alt_region {
@@ -33,13 +38,63 @@ struct alt_region {
        struct alt_instr *end;
 };
 
-static int __apply_alternatives(void *alt_region)
+/*
+ * Check if the target PC is within an alternative block.
+ */
+static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc)
+{
+       unsigned long replptr;
+
+       if (kernel_text_address(pc))
+               return 1;
+
+       replptr = (unsigned long)ALT_REPL_PTR(alt);
+       if (pc >= replptr && pc <= (replptr + alt->alt_len))
+               return 0;
+
+       /*
+        * Branching into *another* alternate sequence is doomed, and
+        * we're not even trying to fix it up.
+        */
+       BUG();
+}
+
+static u32 get_alt_insn(struct alt_instr *alt, u32 *insnptr, u32 *altinsnptr)
+{
+       u32 insn;
+
+       insn = le32_to_cpu(*altinsnptr);
+
+       if (aarch64_insn_is_branch_imm(insn)) {
+               s32 offset = aarch64_get_branch_offset(insn);
+               unsigned long target;
+
+               target = (unsigned long)altinsnptr + offset;
+
+               /*
+                * If we're branching inside the alternate sequence,
+                * do not rewrite the instruction, as it is already
+                * correct. Otherwise, generate the new instruction.
+                */
+               if (branch_insn_requires_update(alt, target)) {
+                       offset = target - (unsigned long)insnptr;
+                       insn = aarch64_set_branch_offset(insn, offset);
+               }
+       }
+
+       return insn;
+}
+
+static void __apply_alternatives(void *alt_region)
 {
        struct alt_instr *alt;
        struct alt_region *region = alt_region;
-       u8 *origptr, *replptr;
+       u32 *origptr, *replptr;
 
        for (alt = region->begin; alt < region->end; alt++) {
+               u32 insn;
+               int i, nr_inst;
+
                if (!cpus_have_cap(alt->cpufeature))
                        continue;
 
@@ -47,25 +102,51 @@ static int __apply_alternatives(void *alt_region)
 
                pr_info_once("patching kernel code\n");
 
-               origptr = (u8 *)&alt->orig_offset + alt->orig_offset;
-               replptr = (u8 *)&alt->alt_offset + alt->alt_offset;
-               memcpy(origptr, replptr, alt->alt_len);
+               origptr = ALT_ORIG_PTR(alt);
+               replptr = ALT_REPL_PTR(alt);
+               nr_inst = alt->alt_len / sizeof(insn);
+
+               for (i = 0; i < nr_inst; i++) {
+                       insn = get_alt_insn(alt, origptr + i, replptr + i);
+                       *(origptr + i) = cpu_to_le32(insn);
+               }
+
                flush_icache_range((uintptr_t)origptr,
-                                  (uintptr_t)(origptr + alt->alt_len));
+                                  (uintptr_t)(origptr + nr_inst));
        }
-
-       return 0;
 }
 
-void apply_alternatives_all(void)
+/*
+ * We might be patching the stop_machine state machine, so implement a
+ * really simple polling protocol here.
+ */
+static int __apply_alternatives_multi_stop(void *unused)
 {
+       static int patched = 0;
        struct alt_region region = {
                .begin  = __alt_instructions,
                .end    = __alt_instructions_end,
        };
 
+       /* We always have a CPU 0 at this point (__init) */
+       if (smp_processor_id()) {
+               while (!READ_ONCE(patched))
+                       cpu_relax();
+               isb();
+       } else {
+               BUG_ON(patched);
+               __apply_alternatives(&region);
+               /* Barriers provided by the cache flushing */
+               WRITE_ONCE(patched, 1);
+       }
+
+       return 0;
+}
+
+void __init apply_alternatives_all(void)
+{
        /* better not try code patching on a live SMP system */
-       stop_machine(__apply_alternatives, &region, NULL);
+       stop_machine(__apply_alternatives_multi_stop, NULL, cpu_online_mask);
 }
 
 void apply_alternatives(void *start, size_t length)