These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / arch / arm / mm / proc-v7-2level.S

diff --git a/kernel/arch/arm/mm/proc-v7-2level.S b/kernel/arch/arm/mm/proc-v7-2level.S
index 10405b8..c6141a5 100644 (file)
--- a/kernel/arch/arm/mm/proc-v7-2level.S
+++ b/kernel/arch/arm/mm/proc-v7-2level.S
@@ -36,14 +36,16 @@
  *
  *     It is assumed that:
  *     - we are not using split page tables
+ *
+ *     Note that we always need to flush BTAC/BTB if IBE is set
+ *     even on Cortex-A8 revisions not affected by 430973.
+ *     If IBE is not set, the flush BTAC/BTB won't do anything.
  */
 ENTRY(cpu_ca8_switch_mm)
 #ifdef CONFIG_MMU
        mov     r2, #0
-#ifdef CONFIG_ARM_ERRATA_430973
        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 #endif
-#endif
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
        mmid    r1, r1                          @ get mm->context.id
@@ -148,10 +150,10 @@ ENDPROC(cpu_v7_set_pte_ext)
         * Macro for setting up the TTBRx and TTBCR registers.
         * - \ttb0 and \ttb1 updated with the corresponding flags.
         */
-       .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
+       .macro  v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
        mcr     p15, 0, \zero, c2, c0, 2        @ TTB control register
-       ALT_SMP(orr     \ttbr0, \ttbr0, #TTB_FLAGS_SMP)
-       ALT_UP(orr      \ttbr0, \ttbr0, #TTB_FLAGS_UP)
+       ALT_SMP(orr     \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
+       ALT_UP(orr      \ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
        ALT_SMP(orr     \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
        ALT_UP(orr      \ttbr1, \ttbr1, #TTB_FLAGS_UP)
        mcr     p15, 0, \ttbr1, c2, c0, 1       @ load TTB1