These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / arch / arm / mach-rockchip / pm.c

diff --git a/kernel/arch/arm/mach-rockchip/pm.c b/kernel/arch/arm/mach-rockchip/pm.c
index b0dcbe2..bee8c80 100644 (file)
--- a/kernel/arch/arm/mach-rockchip/pm.c
+++ b/kernel/arch/arm/mach-rockchip/pm.c
@@ -45,9 +45,11 @@ static phys_addr_t rk3288_bootram_phy;
 
 static struct regmap *pmu_regmap;
 static struct regmap *sgrf_regmap;
+static struct regmap *grf_regmap;
 
 static u32 rk3288_pmu_pwr_mode_con;
 static u32 rk3288_sgrf_soc_con0;
+static u32 rk3288_sgrf_cpu_con0;
 
 static inline u32 rk3288_l2_config(void)
 {
@@ -66,10 +68,37 @@ static void rk3288_config_bootdata(void)
        rkpm_bootdata_l2ctlr = rk3288_l2_config();
 }
 
+#define GRF_UOC0_CON0                  0x320
+#define GRF_UOC1_CON0                  0x334
+#define GRF_UOC2_CON0                  0x348
+#define GRF_SIDDQ                      BIT(13)
+
+static bool rk3288_slp_disable_osc(void)
+{
+       static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0,
+                                         GRF_UOC2_CON0 };
+       u32 reg, i;
+
+       /*
+        * if any usb phy is still on(GRF_SIDDQ==0), that means we need the
+        * function of usb wakeup, so do not switch to 32khz, since the usb phy
+        * clk does not connect to 32khz osc
+        */
+       for (i = 0; i < ARRAY_SIZE(reg_offset); i++) {
+               regmap_read(grf_regmap, reg_offset[i], &reg);
+               if (!(reg & GRF_SIDDQ))
+                       return false;
+       }
+
+       return true;
+}
+
 static void rk3288_slp_mode_set(int level)
 {
        u32 mode_set, mode_set1;
+       bool osc_disable = rk3288_slp_disable_osc();
 
+       regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);
        regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
 
        regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
@@ -94,9 +123,6 @@ static void rk3288_slp_mode_set(int level)
        regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
                     rk3288_bootram_phy);
 
-       regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
-                    PMU_ARMINT_WAKEUP_EN);
-
        mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
                   BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
                   BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
@@ -107,13 +133,31 @@ static void rk3288_slp_mode_set(int level)
 
        if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
                /* arm off, logic deep sleep */
-               mode_set |= BIT(PMU_BUS_PD_EN) |
+               mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) |
                            BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
-                           BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) |
                            BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
 
+               if (osc_disable)
+                       mode_set |= BIT(PMU_OSC_24M_DIS);
+
                mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
                             BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
+
+               regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+                            PMU_ARMINT_WAKEUP_EN);
+
+               /*
+                * In deep suspend we use PMU_PMU_USE_LF to let the rk3288
+                * switch its main clock supply to the alternative 32kHz
+                * source. Therefore set 30ms on a 32kHz clock for pmic
+                * stabilization. Similar 30ms on 24MHz for the other
+                * mode below.
+                */
+               regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
+
+               /* only wait for stabilization, if we turned the osc off */
+               regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT,
+                                        osc_disable ? 32 * 30 : 0);
        } else {
                /*
                 * arm off, logic normal
@@ -121,6 +165,15 @@ static void rk3288_slp_mode_set(int level)
                 * wakeup will be error
                 */
                mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
+
+               regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+                            PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN);
+
+               /* 30ms on a 24MHz clock for pmic stabilization */
+               regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);
+
+               /* oscillator is still running, so no need to wait */
+               regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0);
        }
 
        regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
@@ -129,6 +182,9 @@ static void rk3288_slp_mode_set(int level)
 
 static void rk3288_slp_mode_set_resume(void)
 {
+       regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0,
+                    rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE);
+
        regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
                     rk3288_pmu_pwr_mode_con);
 
@@ -190,7 +246,14 @@ static int rk3288_suspend_init(struct device_node *np)
                                "rockchip,rk3288-sgrf");
        if (IS_ERR(sgrf_regmap)) {
                pr_err("%s: could not find sgrf regmap\n", __func__);
-               return PTR_ERR(pmu_regmap);
+               return PTR_ERR(sgrf_regmap);
+       }
+
+       grf_regmap = syscon_regmap_lookup_by_compatible(
+                               "rockchip,rk3288-grf");
+       if (IS_ERR(grf_regmap)) {
+               pr_err("%s: could not find grf regmap\n", __func__);
+               return PTR_ERR(grf_regmap);
        }
 
        sram_np = of_find_compatible_node(NULL, NULL,
@@ -221,9 +284,6 @@ static int rk3288_suspend_init(struct device_node *np)
        memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
               rk3288_bootram_sz);
 
-       regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
-       regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
-
        return 0;
 }