These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / arch / arm / boot / dts / mt8135.dtsi

diff --git a/kernel/arch/arm/boot/dts/mt8135.dtsi b/kernel/arch/arm/boot/dts/mt8135.dtsi
index a161e99..cb99b02 100644 (file)
--- a/kernel/arch/arm/boot/dts/mt8135.dtsi
+++ b/kernel/arch/arm/boot/dts/mt8135.dtsi
@@ -12,9 +12,12 @@
  * GNU General Public License for more details.
  */
 
+#include <dt-bindings/clock/mt8135-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset-controller/mt8135-resets.h>
 #include "skeleton64.dtsi"
+#include "mt8135-pinfunc.h"
 
 / {
        compatible = "mediatek,mt8135";
@@ -43,6 +46,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               enable-method = "mediatek,mt81xx-tz-smp";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -69,6 +73,17 @@
                };
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               trustzone-bootinfo@80002000 {
+                       compatible = "mediatek,trustzone-bootinfo";
+                       reg = <0 0x80002000 0 0x1000>;
+               };
+       };
+
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -87,12 +102,26 @@
                        #clock-cells = <0>;
                };
 
-               uart_clk: dummy26m {
+               clk26m: clk26m {
                        compatible = "fixed-clock";
-                       clock-frequency = <26000000>;
                        #clock-cells = <0>;
+                       clock-frequency = <26000000>;
                };
+       };
 
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_LOW)>;
+               clock-frequency = <13000000>;
+               arm,cpu-registers-not-fw-configured;
        };
 
        soc {
@@ -101,6 +130,49 @@
                compatible = "simple-bus";
                ranges;
 
+               topckgen: topckgen@10000000 {
+                       compatible = "mediatek,mt8135-topckgen";
+                       reg = <0 0x10000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               infracfg: infracfg@10001000 {
+                       #reset-cells = <1>;
+                       #clock-cells = <1>;
+                       compatible = "mediatek,mt8135-infracfg", "syscon";
+                       reg = <0 0x10001000 0 0x1000>;
+               };
+
+               pericfg: pericfg@10003000 {
+                       #reset-cells = <1>;
+                       #clock-cells = <1>;
+                       compatible = "mediatek,mt8135-pericfg", "syscon";
+                       reg = <0 0x10003000 0 0x1000>;
+               };
+
+               /*
+                * Pinctrl access register at 0x10005000 and 0x1020c000 through
+                * regmap. Register 0x1000b000 is used by EINT.
+                */
+               pio: pinctrl@10005000 {
+                       compatible = "mediatek,mt8135-pinctrl";
+                       reg = <0 0x1000b000 0 0x1000>;
+                       mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
+                       pins-are-numbered;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               syscfg_pctl_a: syscfg_pctl_a@10005000 {
+                       compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
+                       reg = <0 0x10005000 0 0x1000>;
+               };
+
                timer: timer@10008000 {
                        compatible = "mediatek,mt8135-timer",
                                        "mediatek,mt6577-timer";
@@ -110,6 +182,19 @@
                        clock-names = "system-clk", "rtc-clk";
                };
 
+               pwrap: pwrap@1000f000 {
+                       compatible = "mediatek,mt8135-pwrap";
+                       reg = <0 0x1000f000 0 0x1000>,
+                               <0 0x11017000 0 0x1000>;
+                       reg-names = "pwrap", "pwrap-bridge";
+                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
+                                       <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+                       reset-names = "pwrap", "pwrap-bridge";
+                       clocks = <&clk26m>, <&clk26m>;
+                       clock-names = "spi", "wrap";
+               };
+
                sysirq: interrupt-controller@10200030 {
                        compatible = "mediatek,mt8135-sysirq",
                                     "mediatek,mt6577-sysirq";
@@ -119,6 +204,17 @@
                        reg = <0 0x10200030 0 0x1c>;
                };
 
+               apmixedsys: apmixedsys@10209000 {
+                       compatible = "mediatek,mt8135-apmixedsys";
+                       reg = <0 0x10209000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               syscfg_pctl_b: syscfg_pctl_b@1020c000 {
+                       compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
+                       reg = <0 0x1020c000 0 0x1000>;
+               };
+
                gic: interrupt-controller@10211000 {
                        compatible = "arm,cortex-a15-gic";
                        interrupt-controller;
@@ -134,7 +230,8 @@
                        compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
                        reg = <0 0x11006000 0 0x400>;
                        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
-                       clocks = <&uart_clk>;
+                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+                       clock-names = "baud", "bus";
                        status = "disabled";
                };
 
@@ -142,7 +239,8 @@
                        compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
                        reg = <0 0x11007000 0 0x400>;
                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
-                       clocks = <&uart_clk>;
+                       clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+                       clock-names = "baud", "bus";
                        status = "disabled";
                };
 
@@ -150,7 +248,8 @@
                        compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
                        reg = <0 0x11008000 0 0x400>;
                        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
-                       clocks = <&uart_clk>;
+                       clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+                       clock-names = "baud", "bus";
                        status = "disabled";
                };
 
@@ -158,7 +257,8 @@
                        compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
                        reg = <0 0x11009000 0 0x400>;
                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
-                       clocks = <&uart_clk>;
+                       clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+                       clock-names = "baud", "bus";
                        status = "disabled";
                };