These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / Documentation / devicetree / bindings / clock / renesas,rcar-gen2-cpg-clocks.txt

diff --git a/kernel/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/kernel/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index b02944f..2a9a8ed 100644 (file)
--- a/kernel/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/kernel/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -2,6 +2,8 @@
 
 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
 and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
 
 Required Properties:
 
@@ -10,7 +12,7 @@ Required Properties:
     - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
     - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
     - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
-    - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
+    and "renesas,rcar-gen2-cpg-clocks" as a fallback.
 
   - reg: Base address and length of the memory resource used by the CPG
 
@@ -20,10 +22,18 @@ Required Properties:
   - clock-output-names: The names of the clocks. Supported clocks are "main",
     "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
     "adsp"
+  - #power-domain-cells: Must be 0
 
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
 
-Example
--------
+
+Examples
+--------
+
+  - CPG device node:
 
        cpg_clocks: cpg_clocks@e6150000 {
                compatible = "renesas,r8a7790-cpg-clocks",
@@ -34,4 +44,16 @@ Example
                clock-output-names = "main", "pll0, "pll1", "pll3",
                                     "lb", "qspi", "sdh", "sd0", "sd1", "z",
                                     "rcan", "adsp";
+               #power-domain-cells = <0>;
+       };
+
+
+  - CPG/MSTP Clock Domain member device node:
+
+       thermal@e61f0000 {
+               compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+               reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+               interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+               power-domains = <&cpg_clocks>;
        };