Add spec for time line diagram 59/23959/6
authorYujun Zhang <zhang.yujunz@zte.com.cn>
Fri, 4 Nov 2016 05:40:05 +0000 (13:40 +0800)
committerYujun Zhang <zhang.yujunz@zte.com.cn>
Mon, 7 Nov 2016 07:42:23 +0000 (15:42 +0800)
Change-Id: Ib3f5697f5afee294a469979bc66244f054edb1fd
Signed-off-by: Yujun Zhang <zhang.yujunz@zte.com.cn>
docs/designspec/dashboard.rst

index 555b3a2..60c4720 100644 (file)
@@ -133,3 +133,19 @@ A draft design is as following::
                                              | HIDE COMMON|
                                              +------------+
 
+Time line
+---------
+
+Time line diagram for analysis of time critical performance test::
+
+  +-----------------+-----------+-------------+-------------+-----+
+  |                 |           |             |             |     |
+  +----------------->           |             |             |     |
+  |                 +----------->             |             |     |
+  |                 ? ms        +------------->             |     |
+  |                             ? ms          +------------>+     |
+  |                                           ? ms          ? ms  |
+  |                                                               |
+  +---------------------------------------------------------------+
+
+The time cost between checkpoints shall be displayed in the diagram.