X-Git-Url: https://gerrit.opnfv.org/gerrit/gitweb?a=blobdiff_plain;f=qemu%2Froms%2Fu-boot%2Fboard%2Ftqc%2Ftqm5200%2Fmt48lc16m16a2-75.h;fp=qemu%2Froms%2Fu-boot%2Fboard%2Ftqc%2Ftqm5200%2Fmt48lc16m16a2-75.h;h=3d9979664f3b44a29133d0485736baa3441a9ca5;hb=e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb;hp=0000000000000000000000000000000000000000;hpb=9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00;p=kvmfornfv.git

diff --git a/qemu/roms/u-boot/board/tqc/tqm5200/mt48lc16m16a2-75.h b/qemu/roms/u-boot/board/tqc/tqm5200/mt48lc16m16a2-75.h
new file mode 100644
index 000000000..3d9979664
--- /dev/null
+++ b/qemu/roms/u-boot/board/tqc/tqm5200/mt48lc16m16a2-75.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2	0x8AD70000
+/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */