X-Git-Url: https://gerrit.opnfv.org/gerrit/gitweb?a=blobdiff_plain;f=qemu%2Froms%2Fu-boot%2Fboard%2Ffreescale%2Fp2020come%2Flaw.c;fp=qemu%2Froms%2Fu-boot%2Fboard%2Ffreescale%2Fp2020come%2Flaw.c;h=7048a0823ed6f8fc8d082eb145d00b21878626e2;hb=e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb;hp=0000000000000000000000000000000000000000;hpb=9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00;p=kvmfornfv.git

diff --git a/qemu/roms/u-boot/board/freescale/p2020come/law.c b/qemu/roms/u-boot/board/freescale/p2020come/law.c
new file mode 100644
index 000000000..7048a0823
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/p2020come/law.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Create a dummy LAW entry for the DDR SDRAM which will be replaced when
+ * the DDR SPD setup code runs.
+ *
+ * This table would be empty, except that it is used before the BSS section is
+ * initialized, and therefore must have at least one entry to push it into
+ * the DATA section.
+ */
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);