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diff --git a/qemu/roms/u-boot/arch/mips/include/asm/cache.h b/qemu/roms/u-boot/arch/mips/include/asm/cache.h
new file mode 100644
index 000000000..0dfb54ef4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/mips/include/asm/cache.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MIPS_CACHE_H__
+#define __MIPS_CACHE_H__
+
+/*
+ * The maximum L1 data cache line size on MIPS seems to be 128 bytes.  We use
+ * that as a default for aligning DMA buffers unless the board config has
+ * specified another cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	128
+#endif
+
+#endif /* __MIPS_CACHE_H__ */