X-Git-Url: https://gerrit.opnfv.org/gerrit/gitweb?a=blobdiff_plain;f=qemu%2Froms%2Fu-boot%2Farch%2Fmicroblaze%2Fcpu%2Fu-boot-spl.lds;fp=qemu%2Froms%2Fu-boot%2Farch%2Fmicroblaze%2Fcpu%2Fu-boot-spl.lds;h=96353cd96ca7903c08ea0f9fb1db8fadf83cfd59;hb=e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb;hp=0000000000000000000000000000000000000000;hpb=9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00;p=kvmfornfv.git

diff --git a/qemu/roms/u-boot/arch/microblaze/cpu/u-boot-spl.lds b/qemu/roms/u-boot/arch/microblaze/cpu/u-boot-spl.lds
new file mode 100644
index 000000000..96353cd96
--- /dev/null
+++ b/qemu/roms/u-boot/arch/microblaze/cpu/u-boot-spl.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		arch/microblaze/cpu/start.o (.text)
+		*(.text)
+		*(.text.*)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		*(.data.*)
+		__data_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.sbss)
+		*(.scommon)
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+	__end = . ;
+}
+
+#if defined(CONFIG_SPL_MAX_FOOTPRINT)
+ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+        "SPL image plus BSS too big");
+#endif