X-Git-Url: https://gerrit.opnfv.org/gerrit/gitweb?a=blobdiff_plain;f=kernel%2Fdrivers%2Fstaging%2Frtl8192e%2Frtl8192e%2Fr8192E_phy.c;fp=kernel%2Fdrivers%2Fstaging%2Frtl8192e%2Frtl8192e%2Fr8192E_phy.c;h=0b407feb54073348a3a551506723a4553ea89f54;hb=e09b41010ba33a20a87472ee821fa407a5b8da36;hp=4664a4fd1e48cd8b9cfa1c894ed481c1b8cc2612;hpb=f93b97fd65072de626c074dbe099a1fff05ce060;p=kvmfornfv.git diff --git a/kernel/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c b/kernel/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c index 4664a4fd1..0b407feb5 100644 --- a/kernel/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c +++ b/kernel/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c @@ -6,10 +6,6 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * * The full GNU General Public License is included in this distribution in the * file called LICENSE. * @@ -17,6 +13,7 @@ * wlanfae ******************************************************************************/ +#include #include "rtl_core.h" #include "r8192E_hw.h" #include "r8192E_phyreg.h" @@ -46,25 +43,20 @@ static u32 RF_CHANNEL_TABLE_ZEBRA[] = { /*************************Define local function prototype**********************/ -static u32 phy_FwRFSerialRead(struct net_device *dev, - enum rf90_radio_path eRFPath, - u32 Offset); -static void phy_FwRFSerialWrite(struct net_device *dev, - enum rf90_radio_path eRFPath, - u32 Offset, u32 Data); +static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset); +static void _rtl92e_phy_rf_fw_write(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset, + u32 Data); -static u32 rtl8192_CalculateBitShift(u32 dwBitMask) +static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask) { - u32 i; - - for (i = 0; i <= 31; i++) { - if (((dwBitMask >> i) & 0x1) == 1) - break; - } - return i; + if (!dwBitMask) + return 32; + return ffs(dwBitMask) - 1; } -u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) +u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath) { u8 ret = 1; struct r8192_priv *priv = rtllib_priv(dev); @@ -80,34 +72,35 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) return ret; } -void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, - u32 dwData) +void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, + u32 dwData) { u32 OriginalValue, BitShift, NewValue; if (dwBitMask != bMaskDWord) { - OriginalValue = read_nic_dword(dev, dwRegAddr); - BitShift = rtl8192_CalculateBitShift(dwBitMask); + OriginalValue = rtl92e_readl(dev, dwRegAddr); + BitShift = _rtl92e_calculate_bit_shift(dwBitMask); NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); - write_nic_dword(dev, dwRegAddr, NewValue); + rtl92e_writel(dev, dwRegAddr, NewValue); } else - write_nic_dword(dev, dwRegAddr, dwData); + rtl92e_writel(dev, dwRegAddr, dwData); } -u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) +u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) { u32 Ret = 0, OriginalValue, BitShift; - OriginalValue = read_nic_dword(dev, dwRegAddr); - BitShift = rtl8192_CalculateBitShift(dwBitMask); + OriginalValue = rtl92e_readl(dev, dwRegAddr); + BitShift = _rtl92e_calculate_bit_shift(dwBitMask); Ret = (OriginalValue & dwBitMask) >> BitShift; return Ret; } -static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, - enum rf90_radio_path eRFPath, u32 Offset) + +static u32 _rtl92e_phy_rf_read(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset) { struct r8192_priv *priv = rtllib_priv(dev); u32 ret = 0; @@ -117,19 +110,19 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, Offset &= 0x3f; if (priv->rf_chip == RF_8256) { - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); if (Offset >= 31) { priv->RfReg0Value[eRFPath] |= 0x140; - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath]<<16)); + rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath]<<16)); NewOffset = Offset - 30; } else if (Offset >= 16) { priv->RfReg0Value[eRFPath] |= 0x100; priv->RfReg0Value[eRFPath] &= (~0x40); - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath]<<16)); + rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath]<<16)); NewOffset = Offset - 15; } else @@ -139,23 +132,23 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, "check RF type here, need to be 8256\n"); NewOffset = Offset; } - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, - NewOffset); - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); + rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, + NewOffset); + rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); + rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); mdelay(1); - ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, - bLSSIReadBackData); + ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack, + bLSSIReadBackData); if (priv->rf_chip == RF_8256) { priv->RfReg0Value[eRFPath] &= 0xebf; - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); } @@ -163,9 +156,9 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, } -static void rtl8192_phy_RFSerialWrite(struct net_device *dev, - enum rf90_radio_path eRFPath, u32 Offset, - u32 Data) +static void _rtl92e_phy_rf_write(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset, + u32 Data) { struct r8192_priv *priv = rtllib_priv(dev); u32 DataAndAddr = 0, NewOffset = 0; @@ -173,20 +166,20 @@ static void rtl8192_phy_RFSerialWrite(struct net_device *dev, Offset &= 0x3f; if (priv->rf_chip == RF_8256) { - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); if (Offset >= 31) { priv->RfReg0Value[eRFPath] |= 0x140; - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); NewOffset = Offset - 30; } else if (Offset >= 16) { priv->RfReg0Value[eRFPath] |= 0x100; priv->RfReg0Value[eRFPath] &= (~0x40); - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); NewOffset = Offset - 15; } else NewOffset = Offset; @@ -198,7 +191,7 @@ static void rtl8192_phy_RFSerialWrite(struct net_device *dev, DataAndAddr = (Data<<16) | (NewOffset&0x3f); - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); + rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); if (Offset == 0x0) priv->RfReg0Value[eRFPath] = Data; @@ -206,23 +199,21 @@ static void rtl8192_phy_RFSerialWrite(struct net_device *dev, if (priv->rf_chip == RF_8256) { if (Offset != 0) { priv->RfReg0Value[eRFPath] &= 0xebf; - rtl8192_setBBreg( - dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); } - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); } } -void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, - u32 RegAddr, u32 BitMask, u32 Data) +void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask, u32 Data) { struct r8192_priv *priv = rtllib_priv(dev); u32 Original_Value, BitShift, New_Value; - if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + if (!rtl92e_is_legal_rf_path(dev, eRFPath)) return; if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) return; @@ -230,58 +221,57 @@ void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); if (priv->Rf_Mode == RF_OP_By_FW) { if (BitMask != bMask12Bits) { - Original_Value = phy_FwRFSerialRead(dev, eRFPath, - RegAddr); - BitShift = rtl8192_CalculateBitShift(BitMask); + Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, + RegAddr); + BitShift = _rtl92e_calculate_bit_shift(BitMask); New_Value = (((Original_Value) & (~BitMask)) | (Data << BitShift)); - phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); + _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, + New_Value); } else - phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); + _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data); udelay(200); } else { if (BitMask != bMask12Bits) { - Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, - RegAddr); - BitShift = rtl8192_CalculateBitShift(BitMask); + Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, + RegAddr); + BitShift = _rtl92e_calculate_bit_shift(BitMask); New_Value = (((Original_Value) & (~BitMask)) | (Data << BitShift)); - rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, - New_Value); + _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value); } else - rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); + _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data); } } -u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, - u32 RegAddr, u32 BitMask) +u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask) { u32 Original_Value, Readback_Value, BitShift; struct r8192_priv *priv = rtllib_priv(dev); - if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + if (!rtl92e_is_legal_rf_path(dev, eRFPath)) return 0; if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) return 0; down(&priv->rf_sem); if (priv->Rf_Mode == RF_OP_By_FW) { - Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr); udelay(200); } else { - Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, - RegAddr); + Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr); } - BitShift = rtl8192_CalculateBitShift(BitMask); + BitShift = _rtl92e_calculate_bit_shift(BitMask); Readback_Value = (Original_Value & BitMask) >> BitShift; up(&priv->rf_sem); return Readback_Value; } -static u32 phy_FwRFSerialRead(struct net_device *dev, - enum rf90_radio_path eRFPath, u32 Offset) +static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset) { u32 Data = 0; u8 time = 0; @@ -289,26 +279,26 @@ static u32 phy_FwRFSerialRead(struct net_device *dev, Data |= ((Offset & 0xFF) << 12); Data |= ((eRFPath & 0x3) << 20); Data |= 0x80000000; - while (read_nic_dword(dev, QPNR)&0x80000000) { + while (rtl92e_readl(dev, QPNR) & 0x80000000) { if (time++ < 100) udelay(10); else break; } - write_nic_dword(dev, QPNR, Data); - while (read_nic_dword(dev, QPNR) & 0x80000000) { + rtl92e_writel(dev, QPNR, Data); + while (rtl92e_readl(dev, QPNR) & 0x80000000) { if (time++ < 100) udelay(10); else return 0; } - return read_nic_dword(dev, RF_DATA); + return rtl92e_readl(dev, RF_DATA); } -static void phy_FwRFSerialWrite(struct net_device *dev, - enum rf90_radio_path eRFPath, - u32 Offset, u32 Data) +static void _rtl92e_phy_rf_fw_write(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset, + u32 Data) { u8 time = 0; @@ -317,18 +307,18 @@ static void phy_FwRFSerialWrite(struct net_device *dev, Data |= 0x400000; Data |= 0x80000000; - while (read_nic_dword(dev, QPNR) & 0x80000000) { + while (rtl92e_readl(dev, QPNR) & 0x80000000) { if (time++ < 100) udelay(10); else break; } - write_nic_dword(dev, QPNR, Data); + rtl92e_writel(dev, QPNR, Data); } -void rtl8192_phy_configmac(struct net_device *dev) +void rtl92e_config_mac(struct net_device *dev) { u32 dwArrayLen = 0, i = 0; u32 *pdwArray = NULL; @@ -350,14 +340,14 @@ void rtl8192_phy_configmac(struct net_device *dev) pdwArray[i], pdwArray[i+1], pdwArray[i+2]); if (pdwArray[i] == 0x318) pdwArray[i+2] = 0x00000800; - rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], - pdwArray[i+2]); + rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1], + pdwArray[i+2]); } return; } -void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) +static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType) { int i; u32 *Rtl819XPHY_REGArray_Table = NULL; @@ -377,9 +367,9 @@ void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) if (ConfigType == BaseBand_Config_PHY_REG) { for (i = 0; i < PHY_REGArrayLen; i += 2) { - rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], - bMaskDWord, - Rtl819XPHY_REGArray_Table[i+1]); + rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i], + bMaskDWord, + Rtl819XPHY_REGArray_Table[i+1]); RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n", i, Rtl819XPHY_REGArray_Table[i], @@ -387,9 +377,9 @@ void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) } } else if (ConfigType == BaseBand_Config_AGC_TAB) { for (i = 0; i < AGCTAB_ArrayLen; i += 2) { - rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], - bMaskDWord, - Rtl819XAGCTAB_Array_Table[i+1]); + rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i], + bMaskDWord, + Rtl819XAGCTAB_Array_Table[i+1]); RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n", i, Rtl819XAGCTAB_Array_Table[i], @@ -398,7 +388,7 @@ void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) } } -static void rtl8192_InitBBRFRegDef(struct net_device *dev) +static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); @@ -489,9 +479,8 @@ static void rtl8192_InitBBRFRegDef(struct net_device *dev) } -bool rtl8192_phy_checkBBAndRF(struct net_device *dev, - enum hw90_block CheckBlock, - enum rf90_radio_path eRFPath) +bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock, + enum rf90_radio_path eRFPath) { bool ret = true; u32 i, CheckTimes = 4, dwRegRead = 0; @@ -504,29 +493,31 @@ bool rtl8192_phy_checkBBAndRF(struct net_device *dev, WriteAddr[HW90_BLOCK_RF] = 0x3; RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, CheckBlock); + + if (CheckBlock == HW90_BLOCK_MAC) { + netdev_warn(dev, "%s(): No checks available for MAC block.\n", + __func__); + return ret; + } + for (i = 0; i < CheckTimes; i++) { switch (CheckBlock) { - case HW90_BLOCK_MAC: - RT_TRACE(COMP_ERR, - "PHY_CheckBBRFOK(): Never Write 0x100 here!"); - break; - case HW90_BLOCK_PHY0: case HW90_BLOCK_PHY1: - write_nic_dword(dev, WriteAddr[CheckBlock], - WriteData[i]); - dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); + rtl92e_writel(dev, WriteAddr[CheckBlock], + WriteData[i]); + dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]); break; case HW90_BLOCK_RF: WriteData[i] &= 0xfff; - rtl8192_phy_SetRFReg(dev, eRFPath, - WriteAddr[HW90_BLOCK_RF], - bMask12Bits, WriteData[i]); + rtl92e_set_rf_reg(dev, eRFPath, + WriteAddr[HW90_BLOCK_RF], + bMask12Bits, WriteData[i]); mdelay(10); - dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, - WriteAddr[HW90_BLOCK_RF], - bMaskDWord); + dwRegRead = rtl92e_get_rf_reg(dev, eRFPath, + WriteAddr[HW90_BLOCK_RF], + bMaskDWord); mdelay(10); break; @@ -537,9 +528,7 @@ bool rtl8192_phy_checkBBAndRF(struct net_device *dev, if (dwRegRead != WriteData[i]) { - RT_TRACE(COMP_ERR, - "====>error=====dwRegRead: %x, WriteData: %x\n", - dwRegRead, WriteData[i]); + netdev_warn(dev, "%s(): Check failed.\n", __func__); ret = false; break; } @@ -548,38 +537,38 @@ bool rtl8192_phy_checkBBAndRF(struct net_device *dev, return ret; } -static bool rtl8192_BB_Config_ParaFile(struct net_device *dev) +static bool _rtl92e_bb_config_para_file(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); bool rtStatus = true; u8 bRegValue = 0, eCheckItem = 0; u32 dwRegValue = 0; - bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); - write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); + bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET); + rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); - dwRegValue = read_nic_dword(dev, CPU_GEN); - write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); + dwRegValue = rtl92e_readl(dev, CPU_GEN); + rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { - rtStatus = rtl8192_phy_checkBBAndRF(dev, - (enum hw90_block)eCheckItem, - (enum rf90_radio_path)0); + rtStatus = rtl92e_check_bb_and_rf(dev, + (enum hw90_block)eCheckItem, + (enum rf90_radio_path)0); if (!rtStatus) { RT_TRACE((COMP_ERR | COMP_PHY), - "PHY_RF8256_Config():Check PHY%d Fail!!\n", + "rtl92e_config_rf():Check PHY%d Fail!!\n", eCheckItem-1); return rtStatus; } } - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); - rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); + rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); + _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG); - dwRegValue = read_nic_dword(dev, CPU_GEN); - write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); + dwRegValue = rtl92e_readl(dev, CPU_GEN); + rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); - rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); + _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB); if (priv->IC_Cut > VERSION_8190_BD) { if (priv->rf_type == RF_2T4R) @@ -588,57 +577,57 @@ static bool rtl8192_BB_Config_ParaFile(struct net_device *dev) priv->AntennaTxPwDiff[0]); else dwRegValue = 0x0; - rtl8192_setBBreg(dev, rFPGA0_TxGainStage, - (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); + rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, + (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); dwRegValue = priv->CrystalCap; - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, - dwRegValue); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, + dwRegValue); } return rtStatus; } -bool rtl8192_BBConfig(struct net_device *dev) +bool rtl92e_config_bb(struct net_device *dev) { - rtl8192_InitBBRFRegDef(dev); - return rtl8192_BB_Config_ParaFile(dev); + _rtl92e_init_bb_rf_reg_def(dev); + return _rtl92e_bb_config_para_file(dev); } -void rtl8192_phy_getTxPower(struct net_device *dev) +void rtl92e_get_tx_power(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); priv->MCSTxPowerLevelOriginalOffset[0] = - read_nic_dword(dev, rTxAGC_Rate18_06); + rtl92e_readl(dev, rTxAGC_Rate18_06); priv->MCSTxPowerLevelOriginalOffset[1] = - read_nic_dword(dev, rTxAGC_Rate54_24); + rtl92e_readl(dev, rTxAGC_Rate54_24); priv->MCSTxPowerLevelOriginalOffset[2] = - read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); + rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00); priv->MCSTxPowerLevelOriginalOffset[3] = - read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); + rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04); priv->MCSTxPowerLevelOriginalOffset[4] = - read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); + rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08); priv->MCSTxPowerLevelOriginalOffset[5] = - read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); + rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12); - priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); - priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); - priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); - priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); + priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1); + priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1); + priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1); + priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1); RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", - priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], - priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); + priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], + priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); - priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); - priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); + priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3); + priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2); RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", rOFDM0_RxDetector3, priv->framesync); - priv->SifsTime = read_nic_word(dev, SIFS); + priv->SifsTime = rtl92e_readw(dev, SIFS); } -void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) +void rtl92e_set_tx_power(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); u8 powerlevel = 0, powerlevelOFDM24G = 0; @@ -671,27 +660,27 @@ void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]); - rtl8192_setBBreg(dev, rFPGA0_TxGainStage, - (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); + rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, + (bXBTxAGC|bXCTxAGC|bXDTxAGC), + u4RegValue); } } switch (priv->rf_chip) { case RF_8225: break; case RF_8256: - PHY_SetRF8256CCKTxPower(dev, powerlevel); - PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); + rtl92e_set_cck_tx_power(dev, powerlevel); + rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); break; case RF_8258: break; default: - RT_TRACE(COMP_ERR, "unknown rf chip in function %s()\n", - __func__); + netdev_err(dev, "Invalid RF Chip ID.\n"); break; } } -bool rtl8192_phy_RFConfig(struct net_device *dev) +bool rtl92e_config_phy(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); bool rtStatus = true; @@ -700,7 +689,7 @@ bool rtl8192_phy_RFConfig(struct net_device *dev) case RF_8225: break; case RF_8256: - rtStatus = PHY_RF8256_Config(dev); + rtStatus = rtl92e_config_rf(dev); break; case RF_8258: @@ -709,18 +698,13 @@ bool rtl8192_phy_RFConfig(struct net_device *dev) break; default: - RT_TRACE(COMP_ERR, "error chip id\n"); + netdev_err(dev, "Invalid RF Chip ID.\n"); break; } return rtStatus; } -void rtl8192_phy_updateInitGain(struct net_device *dev) -{ -} - -u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, - enum rf90_radio_path eRFPath) +u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath) { int i; @@ -732,10 +716,9 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, msleep(100); continue; } - rtl8192_phy_SetRFReg(dev, eRFPath, - Rtl819XRadioA_Array[i], - bMask12Bits, - Rtl819XRadioA_Array[i+1]); + rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i], + bMask12Bits, + Rtl819XRadioA_Array[i+1]); } break; @@ -745,10 +728,9 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, msleep(100); continue; } - rtl8192_phy_SetRFReg(dev, eRFPath, - Rtl819XRadioB_Array[i], - bMask12Bits, - Rtl819XRadioB_Array[i+1]); + rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i], + bMask12Bits, + Rtl819XRadioB_Array[i+1]); } break; @@ -758,22 +740,21 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, msleep(100); continue; } - rtl8192_phy_SetRFReg(dev, eRFPath, - Rtl819XRadioC_Array[i], - bMask12Bits, - Rtl819XRadioC_Array[i+1]); + rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i], + bMask12Bits, + Rtl819XRadioC_Array[i+1]); } break; case RF90_PATH_D: for (i = 0; i < RadioD_ArrayLength; i += 2) { if (Rtl819XRadioD_Array[i] == 0xfe) { - msleep(100); - continue; + msleep(100); + continue; } - rtl8192_phy_SetRFReg(dev, eRFPath, - Rtl819XRadioD_Array[i], bMask12Bits, - Rtl819XRadioD_Array[i+1]); + rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i], + bMask12Bits, + Rtl819XRadioD_Array[i+1]); } break; @@ -784,7 +765,8 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, return 0; } -static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) + +static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; @@ -795,35 +777,32 @@ static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) break; case RF_8256: - PHY_SetRF8256CCKTxPower(dev, powerlevel); - PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); + rtl92e_set_cck_tx_power(dev, powerlevel); + rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); break; case RF_8258: break; default: - RT_TRACE(COMP_ERR, - "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); + netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__); break; } } -static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, - u32 CmdTableIdx, u32 CmdTableSz, - enum sw_chnl_cmd_id CmdID, - u32 Para1, u32 Para2, u32 msDelay) +static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev, + struct sw_chnl_cmd *CmdTable, + u32 CmdTableIdx, u32 CmdTableSz, + enum sw_chnl_cmd_id CmdID, + u32 Para1, u32 Para2, u32 msDelay) { struct sw_chnl_cmd *pCmd; if (CmdTable == NULL) { - RT_TRACE(COMP_ERR, - "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); + netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__); return false; } if (CmdTableIdx >= CmdTableSz) { - RT_TRACE(COMP_ERR, - "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", - CmdTableIdx, CmdTableSz); + netdev_err(dev, "%s(): Invalid index requested.\n", __func__); return false; } @@ -836,8 +815,8 @@ static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, return true; } -static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, - u8 *stage, u8 *step, u32 *delay) +static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel, + u8 *stage, u8 *step, u32 *delay) { struct r8192_priv *priv = rtllib_priv(dev); struct rtllib_device *ieee = priv->rtllib; @@ -851,69 +830,79 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, __func__, *stage, *step, channel); if (!rtllib_legal_channel(priv->rtllib, channel)) { - RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", - channel); + netdev_err(dev, "Invalid channel requested: %d\n", channel); return true; } { PreCommonCmdCnt = 0; - rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd, - PreCommonCmdCnt++, - MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, - 0, 0, 0); - rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd, - PreCommonCmdCnt++, - MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); + _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, + PreCommonCmdCnt++, + MAX_PRECMD_CNT, + CmdID_SetTxPowerLevel, + 0, 0, 0); + _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, + PreCommonCmdCnt++, + MAX_PRECMD_CNT, CmdID_End, + 0, 0, 0); PostCommonCmdCnt = 0; - rtl8192_phy_SetSwChnlCmdArray(ieee->PostCommonCmd, - PostCommonCmdCnt++, - MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); + _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd, + PostCommonCmdCnt++, + MAX_POSTCMD_CNT, CmdID_End, + 0, 0, 0); RfDependCmdCnt = 0; switch (priv->rf_chip) { case RF_8225: if (!(channel >= 1 && channel <= 14)) { - RT_TRACE(COMP_ERR, - "illegal channel for Zebra 8225: %d\n", - channel); + netdev_err(dev, + "Invalid channel requested for 8225: %d\n", + channel); return false; } - rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, - RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, - RF_CHANNEL_TABLE_ZEBRA[channel], 10); - rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, - RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); + _rtl92e_phy_set_sw_chnl_cmd_array(dev, + ieee->RfDependCmd, + RfDependCmdCnt++, + MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, + rZebra1_Channel, + RF_CHANNEL_TABLE_ZEBRA[channel], + 10); + _rtl92e_phy_set_sw_chnl_cmd_array(dev, + ieee->RfDependCmd, + RfDependCmdCnt++, + MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); break; case RF_8256: if (!(channel >= 1 && channel <= 14)) { - RT_TRACE(COMP_ERR, - "illegal channel for Zebra 8256: %d\n", - channel); + netdev_err(dev, + "Invalid channel requested for 8256: %d\n", + channel); return false; } - rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, - RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, channel, - 10); - rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, - - RfDependCmdCnt++, - MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); + _rtl92e_phy_set_sw_chnl_cmd_array(dev, + ieee->RfDependCmd, + RfDependCmdCnt++, + MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, + rZebra1_Channel, + channel, 10); + _rtl92e_phy_set_sw_chnl_cmd_array(dev, + ieee->RfDependCmd, + RfDependCmdCnt++, + MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); break; case RF_8258: break; default: - RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", - priv->rf_chip); + netdev_warn(dev, "Unknown RF Chip ID\n"); return false; } @@ -944,24 +933,25 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, switch (CurrentCmd->CmdID) { case CmdID_SetTxPowerLevel: if (priv->IC_Cut > (u8)VERSION_8190_BD) - rtl8192_SetTxPowerLevel(dev, channel); + _rtl92e_set_tx_power_level(dev, + channel); break; case CmdID_WritePortUlong: - write_nic_dword(dev, CurrentCmd->Para1, - CurrentCmd->Para2); + rtl92e_writel(dev, CurrentCmd->Para1, + CurrentCmd->Para2); break; case CmdID_WritePortUshort: - write_nic_word(dev, CurrentCmd->Para1, - (u16)CurrentCmd->Para2); + rtl92e_writew(dev, CurrentCmd->Para1, + (u16)CurrentCmd->Para2); break; case CmdID_WritePortUchar: - write_nic_byte(dev, CurrentCmd->Para1, - (u8)CurrentCmd->Para2); + rtl92e_writeb(dev, CurrentCmd->Para1, + (u8)CurrentCmd->Para2); break; case CmdID_RF_WriteReg: for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) - rtl8192_phy_SetRFReg(dev, + rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); @@ -979,20 +969,22 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, return false; } -static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) +static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); u32 delay = 0; - while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, - &priv->SwChnlStep, &delay)) { + while (!_rtl92e_phy_switch_channel_step(dev, channel, + &priv->SwChnlStage, + &priv->SwChnlStep, &delay)) { if (delay > 0) msleep(delay); if (!priv->up) break; } } -void rtl8192_SwChnl_WorkItem(struct net_device *dev) + +static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); @@ -1002,18 +994,18 @@ void rtl8192_SwChnl_WorkItem(struct net_device *dev) RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, priv->chan, priv); - rtl8192_phy_FinishSwChnlNow(dev , priv->chan); + _rtl92e_phy_switch_channel(dev, priv->chan); RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); } -u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) +u8 rtl92e_set_channel(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); RT_TRACE(COMP_PHY, "=====>%s()\n", __func__); if (!priv->up) { - RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__); + netdev_err(dev, "%s(): Driver is not initialized\n", __func__); return false; } if (priv->SwChnlInProgress) @@ -1024,20 +1016,26 @@ u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) case WIRELESS_MODE_A: case WIRELESS_MODE_N_5G: if (channel <= 14) { - RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); + netdev_warn(dev, + "Channel %d not available in 802.11a.\n", + channel); return false; } break; case WIRELESS_MODE_B: if (channel > 14) { - RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); + netdev_warn(dev, + "Channel %d not available in 802.11b.\n", + channel); return false; } break; case WIRELESS_MODE_G: case WIRELESS_MODE_N_24G: if (channel > 14) { - RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); + netdev_warn(dev, + "Channel %d not available in 802.11g.\n", + channel); return false; } break; @@ -1053,12 +1051,12 @@ u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) priv->SwChnlStep = 0; if (priv->up) - rtl8192_SwChnl_WorkItem(dev); + _rtl92e_phy_switch_channel_work_item(dev); priv->SwChnlInProgress = false; return true; } -static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev) +static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); @@ -1082,13 +1080,13 @@ static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev) if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) { priv->bcck_in_ch14 = true; - dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) { priv->bcck_in_ch14 = false; - dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } else { - dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } break; @@ -1110,19 +1108,19 @@ static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev) if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) { priv->bcck_in_ch14 = true; - dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) { priv->bcck_in_ch14 = false; - dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } else { - dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } break; } } -static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) +static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); @@ -1139,38 +1137,38 @@ static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) priv->Record_CCK_20Mindex = 6; priv->CCK_index = priv->Record_CCK_20Mindex; RT_TRACE(COMP_POWER_TRACKING, - "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", + "20MHz, _rtl92e_cck_tx_power_track_bw_switch_thermal(),CCK_index = %d\n", priv->CCK_index); break; case HT_CHANNEL_WIDTH_20_40: priv->CCK_index = priv->Record_CCK_40Mindex; RT_TRACE(COMP_POWER_TRACKING, - "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", + "40MHz, _rtl92e_cck_tx_power_track_bw_switch_thermal(), CCK_index = %d\n", priv->CCK_index); break; } - dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } -static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) +static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); if (priv->IC_Cut >= IC_VersionCut_D) - CCK_Tx_Power_Track_BW_Switch_TSSI(dev); + _rtl92e_cck_tx_power_track_bw_switch_tssi(dev); else - CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); + _rtl92e_cck_tx_power_track_bw_switch_thermal(dev); } -void rtl8192_SetBWModeWorkItem(struct net_device *dev) +static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); u8 regBwOpMode; RT_TRACE(COMP_SWBW, - "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", + "==>_rtl92e_set_bw_mode_work_item() Switch to %s bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? "20MHz" : "40MHz"); @@ -1180,68 +1178,66 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) return; } if (!priv->up) { - RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__); + netdev_err(dev, "%s(): Driver is not initialized\n", __func__); return; } - regBwOpMode = read_nic_byte(dev, BW_OPMODE); + regBwOpMode = rtl92e_readb(dev, BW_OPMODE); switch (priv->CurrentChannelBW) { case HT_CHANNEL_WIDTH_20: regBwOpMode |= BW_OPMODE_20MHZ; - write_nic_byte(dev, BW_OPMODE, regBwOpMode); + rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); break; case HT_CHANNEL_WIDTH_20_40: regBwOpMode &= ~BW_OPMODE_20MHZ; - write_nic_byte(dev, BW_OPMODE, regBwOpMode); + rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); break; default: - RT_TRACE(COMP_ERR, - "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", - priv->CurrentChannelBW); + netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, + priv->CurrentChannelBW); break; } switch (priv->CurrentChannelBW) { case HT_CHANNEL_WIDTH_20: - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); - rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); + rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); if (!priv->btxpower_tracking) { - write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); - write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); - write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); + rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000); + rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317); + rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204); } else { - CCK_Tx_Power_Track_BW_Switch(dev); + _rtl92e_cck_tx_power_track_bw_switch(dev); } - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); break; case HT_CHANNEL_WIDTH_20_40: - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); - rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); + rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); if (!priv->btxpower_tracking) { - write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); - write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); - write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); + rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000); + rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e); + rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409); } else { - CCK_Tx_Power_Track_BW_Switch(dev); + _rtl92e_cck_tx_power_track_bw_switch(dev); } - rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, - (priv->nCur40MhzPrimeSC>>1)); - rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, - priv->nCur40MhzPrimeSC); + rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand, + (priv->nCur40MhzPrimeSC>>1)); + rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00, + priv->nCur40MhzPrimeSC); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); break; default: - RT_TRACE(COMP_ERR, - "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", - priv->CurrentChannelBW); + netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, + priv->CurrentChannelBW); break; } @@ -1251,7 +1247,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) break; case RF_8256: - PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); + rtl92e_set_bandwidth(dev, priv->CurrentChannelBW); break; case RF_8258: @@ -1261,7 +1257,8 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) break; default: - RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); + netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__, + priv->rf_chip); break; } @@ -1271,8 +1268,8 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); } -void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, - enum ht_extchnl_offset Offset) +void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width Bandwidth, + enum ht_extchnl_offset Offset) { struct r8192_priv *priv = rtllib_priv(dev); @@ -1292,11 +1289,11 @@ void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, else priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - rtl8192_SetBWModeWorkItem(dev); + _rtl92e_set_bw_mode_work_item(dev); } -void InitialGain819xPci(struct net_device *dev, u8 Operation) +void rtl92e_init_gain(struct net_device *dev, u8 Operation) { #define SCAN_RX_INITIAL_GAIN 0x17 #define POWER_DETECTION_TH 0x08 @@ -1313,21 +1310,21 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) BitMask = bMaskByte0; if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); priv->initgain_backup.xaagccore1 = - (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, - BitMask); + (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, + BitMask); priv->initgain_backup.xbagccore1 = - (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, - BitMask); + (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, + BitMask); priv->initgain_backup.xcagccore1 = - (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, - BitMask); + (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, + BitMask); priv->initgain_backup.xdagccore1 = - (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, - BitMask); + (u8)rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1, + BitMask); BitMask = bMaskByte2; - priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, + priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev, rCCK0_CCA, BitMask); RT_TRACE(COMP_SCAN, @@ -1348,13 +1345,13 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", initial_gain); - write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain); + rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain); + rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain); + rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain); RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", POWER_DETECTION_TH); - write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); + rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH); break; case IG_Restore: RT_TRACE(COMP_SCAN, @@ -1362,18 +1359,18 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) BitMask = 0x7f; if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); - rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, + rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); - rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, + rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); - rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, + rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); - rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, + rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); BitMask = bMaskByte2; - rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, + rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); RT_TRACE(COMP_SCAN, @@ -1392,12 +1389,12 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) "Scan BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca); - rtl8192_phy_setTxPower(dev, + rtl92e_set_tx_power(dev, priv->rtllib->current_network.channel); if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); + rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); break; default: RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); @@ -1406,22 +1403,22 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) } } -void PHY_SetRtl8192eRfOff(struct net_device *dev) +void rtl92e_set_rf_off(struct net_device *dev) { - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); - rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); - rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); - write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07); + rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); + rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); + rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); + rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07); } -static bool SetRFPowerState8190(struct net_device *dev, - enum rt_rf_power_state eRFPowerState) +static bool _rtl92e_set_rf_power_state(struct net_device *dev, + enum rt_rf_power_state eRFPowerState) { struct r8192_priv *priv = rtllib_priv(dev); struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) @@ -1432,14 +1429,15 @@ static bool SetRFPowerState8190(struct net_device *dev, if (priv->SetRFPowerStateInProgress) return false; - RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); + RT_TRACE(COMP_PS, "===========> _rtl92e_set_rf_power_state()!\n"); priv->SetRFPowerStateInProgress = true; switch (priv->rf_chip) { case RF_8256: switch (eRFPowerState) { case eRfOn: - RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n"); + RT_TRACE(COMP_PS, + "_rtl92e_set_rf_power_state() eRfOn!\n"); if ((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { bool rtstatus = true; @@ -1448,13 +1446,13 @@ static bool SetRFPowerState8190(struct net_device *dev, do { InitilizeCount--; priv->RegRfOff = false; - rtstatus = NicIFEnableNIC(dev); + rtstatus = rtl92e_enable_nic(dev); } while (!rtstatus && (InitilizeCount > 0)); if (!rtstatus) { - RT_TRACE(COMP_ERR, - "%s():Initialize Adapter fail,return\n", - __func__); + netdev_err(dev, + "%s(): Failed to initialize Adapter.\n", + __func__); priv->SetRFPowerStateInProgress = false; return false; } @@ -1462,24 +1460,24 @@ static bool SetRFPowerState8190(struct net_device *dev, RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); } else { - write_nic_byte(dev, ANAPAR, 0x37); + rtl92e_writeb(dev, ANAPAR, 0x37); mdelay(1); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); priv->bHwRfOffAction = 0; - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, - BIT4, 0x1); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, - 0x300, 0x3); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, - 0x18, 0x3); - rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, - 0x3); - rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, - 0x3); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, - 0x60, 0x3); + rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, + BIT4, 0x1); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, + 0x300, 0x3); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, + 0x18, 0x3); + rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, + 0x3, 0x3); + rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, + 0x3, 0x3); + rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, + 0x60, 0x3); } @@ -1506,18 +1504,18 @@ static bool SetRFPowerState8190(struct net_device *dev, if (i >= MAX_DOZE_WAITING_TIMES_9x) { RT_TRACE(COMP_POWER, - "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n", + "\n\n\n TimeOut!! _rtl92e_set_rf_power_state(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); break; } } - PHY_SetRtl8192eRfOff(dev); + rtl92e_set_rf_off(dev); break; case eRfOff: RT_TRACE(COMP_PS, - "SetRFPowerState8190() eRfOff/Sleep !\n"); + "_rtl92e_set_rf_power_state() eRfOff/Sleep !\n"); for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { ring = &priv->tx_ring[QueueID]; @@ -1544,27 +1542,27 @@ static bool SetRFPowerState8190(struct net_device *dev, if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { - NicIFDisableNIC(dev); + rtl92e_disable_nic(dev); RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); } else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC)) { - PHY_SetRtl8192eRfOff(dev); + rtl92e_set_rf_off(dev); } break; default: bResult = false; - RT_TRACE(COMP_ERR, - "SetRFPowerState8190(): unknown state to set: 0x%X!!!\n", - eRFPowerState); + netdev_warn(dev, + "%s(): Unknown state requested: 0x%X.\n", + __func__, eRFPowerState); break; } break; default: - RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); + netdev_warn(dev, "%s(): Unknown RF type\n", __func__); break; } @@ -1576,44 +1574,46 @@ static bool SetRFPowerState8190(struct net_device *dev, break; default: - RT_TRACE(COMP_ERR, - "SetRFPowerState8190(): Unknown RF type\n"); + netdev_warn(dev, "%s(): Unknown RF type\n", __func__); break; } } priv->SetRFPowerStateInProgress = false; - RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", + RT_TRACE(COMP_PS, + "<=========== _rtl92e_set_rf_power_state() bResult = %d!\n", bResult); return bResult; } -bool SetRFPowerState(struct net_device *dev, - enum rt_rf_power_state eRFPowerState) +bool rtl92e_set_rf_power_state(struct net_device *dev, + enum rt_rf_power_state eRFPowerState) { struct r8192_priv *priv = rtllib_priv(dev); bool bResult = false; - RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n", + RT_TRACE(COMP_PS, + "---------> rtl92e_set_rf_power_state(): eRFPowerState(%d)\n", eRFPowerState); if (eRFPowerState == priv->rtllib->eRFPowerState && priv->bHwRfOffAction == 0) { RT_TRACE(COMP_PS, - "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", + "<--------- rtl92e_set_rf_power_state(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); return bResult; } - bResult = SetRFPowerState8190(dev, eRFPowerState); + bResult = _rtl92e_set_rf_power_state(dev, eRFPowerState); - RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", + RT_TRACE(COMP_PS, + "<--------- rtl92e_set_rf_power_state(): bResult(%d)\n", bResult); return bResult; } -void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation) +void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation) { struct r8192_priv *priv = rtllib_priv(dev);