X-Git-Url: https://gerrit.opnfv.org/gerrit/gitweb?a=blobdiff_plain;f=kernel%2Fdrivers%2Fstaging%2Fcomedi%2Fdrivers%2Faddi-data%2Fhwdrv_apci1564.c;fp=kernel%2Fdrivers%2Fstaging%2Fcomedi%2Fdrivers%2Faddi-data%2Fhwdrv_apci1564.c;h=f0c0d58383ca7fb06a8cb88c2da4383689d531cb;hb=e09b41010ba33a20a87472ee821fa407a5b8da36;hp=fa99c8ca4f95093c98f8fb8f37ab8ba6fac63660;hpb=f93b97fd65072de626c074dbe099a1fff05ce060;p=kvmfornfv.git diff --git a/kernel/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c b/kernel/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c index fa99c8ca4..f0c0d5838 100644 --- a/kernel/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c +++ b/kernel/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c @@ -1,22 +1,3 @@ -/* Digital Input IRQ Function Selection */ -#define APCI1564_DI_INT_OR (0 << 1) -#define APCI1564_DI_INT_AND (1 << 1) - -/* Digital Input Interrupt Enable Disable. */ -#define APCI1564_DI_INT_ENABLE 0x4 -#define APCI1564_DI_INT_DISABLE 0xfffffffb - -/* Digital Output Interrupt Enable Disable. */ -#define APCI1564_DO_VCC_INT_ENABLE 0x1 -#define APCI1564_DO_VCC_INT_DISABLE 0xfffffffe -#define APCI1564_DO_CC_INT_ENABLE 0x2 -#define APCI1564_DO_CC_INT_DISABLE 0xfffffffd - -/* TIMER COUNTER WATCHDOG DEFINES */ -#define ADDIDATA_TIMER 0 -#define ADDIDATA_COUNTER 1 -#define ADDIDATA_WATCHDOG 2 - static int apci1564_timer_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, @@ -27,15 +8,16 @@ static int apci1564_timer_insn_config(struct comedi_device *dev, devpriv->tsk_current = current; - /* First Stop The Timer */ + /* Stop the timer */ ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG); - ctrl &= 0xfffff9fe; - /* Stop The Timer */ + ctrl &= ~(ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG | + ADDI_TCW_CTRL_ENA); outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG); if (data[1] == 1) { /* Enable timer int & disable all the other int sources */ - outl(0x02, devpriv->timer + ADDI_TCW_CTRL_REG); + outl(ADDI_TCW_CTRL_IRQ_ENA, + devpriv->timer + ADDI_TCW_CTRL_REG); outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG); outl(0x0, dev->iobase + APCI1564_DO_IRQ_REG); outl(0x0, dev->iobase + APCI1564_WDOG_IRQ_REG); @@ -59,9 +41,11 @@ static int apci1564_timer_insn_config(struct comedi_device *dev, outl(data[3], devpriv->timer + ADDI_TCW_RELOAD_REG); ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG); - ctrl &= 0xfff719e2; - ctrl |= (2 << 13) | 0x10; - /* mode 2 */ + ctrl &= ~(ADDI_TCW_CTRL_CNTR_ENA | ADDI_TCW_CTRL_MODE_MASK | + ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG | + ADDI_TCW_CTRL_TIMER_ENA | ADDI_TCW_CTRL_RESET_ENA | + ADDI_TCW_CTRL_WARN_ENA | ADDI_TCW_CTRL_ENA); + ctrl |= ADDI_TCW_CTRL_MODE(2) | ADDI_TCW_CTRL_TIMER_ENA; outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG); return insn->n; @@ -76,13 +60,13 @@ static int apci1564_timer_insn_write(struct comedi_device *dev, unsigned int ctrl; ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG); + ctrl &= ~(ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG); switch (data[1]) { case 0: /* Stop The Timer */ - ctrl &= 0xfffff9fe; + ctrl &= ~ADDI_TCW_CTRL_ENA; break; case 1: /* Enable the Timer */ - ctrl &= 0xfffff9ff; - ctrl |= 0x1; + ctrl |= ADDI_TCW_CTRL_ENA; break; } outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG); @@ -98,7 +82,8 @@ static int apci1564_timer_insn_read(struct comedi_device *dev, struct apci1564_private *devpriv = dev->private; /* Stores the status of the Timer */ - data[0] = inl(devpriv->timer + ADDI_TCW_STATUS_REG) & 0x1; + data[0] = inl(devpriv->timer + ADDI_TCW_STATUS_REG) & + ADDI_TCW_STATUS_OVERFLOW; /* Stores the Actual value of the Timer */ data[1] = inl(devpriv->timer + ADDI_TCW_VAL_REG); @@ -118,35 +103,34 @@ static int apci1564_counter_insn_config(struct comedi_device *dev, devpriv->tsk_current = current; - /* First Stop The Counter */ - ctrl = inl(iobase + ADDI_TCW_CTRL_REG); - ctrl &= 0xfffff9fe; /* Stop The Timer */ + ctrl = inl(iobase + ADDI_TCW_CTRL_REG); + ctrl &= ~(ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG | + ADDI_TCW_CTRL_ENA); outl(ctrl, iobase + ADDI_TCW_CTRL_REG); /* Set the reload value */ outl(data[3], iobase + ADDI_TCW_RELOAD_REG); - /* Set the mode : */ - /* - Disable the hardware */ - /* - Disable the counter mode */ - /* - Disable the warning */ - /* - Disable the reset */ - /* - Disable the timer mode */ - /* - Enable the counter mode */ - - ctrl &= 0xfffc19e2; - ctrl |= 0x80000 | (data[4] << 16); + /* Set the mode */ + ctrl &= ~(ADDI_TCW_CTRL_EXT_CLK_MASK | ADDI_TCW_CTRL_MODE_MASK | + ADDI_TCW_CTRL_TIMER_ENA | ADDI_TCW_CTRL_RESET_ENA | + ADDI_TCW_CTRL_WARN_ENA); + ctrl |= ADDI_TCW_CTRL_CNTR_ENA | ADDI_TCW_CTRL_MODE(data[4]); outl(ctrl, iobase + ADDI_TCW_CTRL_REG); /* Enable or Disable Interrupt */ - ctrl &= 0xfffff9fd; - ctrl |= (data[1] << 1); + if (data[1]) + ctrl |= ADDI_TCW_CTRL_IRQ_ENA; + else + ctrl &= ~ADDI_TCW_CTRL_IRQ_ENA; outl(ctrl, iobase + ADDI_TCW_CTRL_REG); /* Set the Up/Down selection */ - ctrl &= 0xfffbf9ff; - ctrl |= (data[6] << 18); + if (data[6]) + ctrl |= ADDI_TCW_CTRL_CNT_UP; + else + ctrl &= ~ADDI_TCW_CTRL_CNT_UP; outl(ctrl, iobase + ADDI_TCW_CTRL_REG); return insn->n; @@ -163,17 +147,16 @@ static int apci1564_counter_insn_write(struct comedi_device *dev, unsigned int ctrl; ctrl = inl(iobase + ADDI_TCW_CTRL_REG); + ctrl &= ~(ADDI_TCW_CTRL_GATE | ADDI_TCW_CTRL_TRIG); switch (data[1]) { case 0: /* Stops the Counter subdevice */ ctrl = 0; break; case 1: /* Start the Counter subdevice */ - ctrl &= 0xfffff9ff; - ctrl |= 0x1; + ctrl |= ADDI_TCW_CTRL_ENA; break; case 2: /* Clears the Counter subdevice */ - ctrl &= 0xfffff9ff; - ctrl |= 0x400; + ctrl |= ADDI_TCW_CTRL_GATE; break; } outl(ctrl, iobase + ADDI_TCW_CTRL_REG); @@ -195,10 +178,10 @@ static int apci1564_counter_insn_read(struct comedi_device *dev, data[0] = inl(iobase + ADDI_TCW_VAL_REG); status = inl(iobase + ADDI_TCW_STATUS_REG); - data[1] = (status >> 1) & 1; /* software trigger status */ - data[2] = (status >> 2) & 1; /* hardware trigger status */ - data[3] = (status >> 3) & 1; /* software clear status */ - data[4] = (status >> 0) & 1; /* overflow status */ + data[1] = (status & ADDI_TCW_STATUS_SOFT_TRIG) ? 1 : 0; + data[2] = (status & ADDI_TCW_STATUS_HARDWARE_TRIG) ? 1 : 0; + data[3] = (status & ADDI_TCW_STATUS_SOFT_CLR) ? 1 : 0; + data[4] = (status & ADDI_TCW_STATUS_OVERFLOW) ? 1 : 0; return insn->n; }