X-Git-Url: https://gerrit.opnfv.org/gerrit/gitweb?a=blobdiff_plain;f=kernel%2Farch%2Fpowerpc%2Fboot%2Fdts%2Ffsl%2Fp5020si-pre.dtsi;h=bfba0b4f1cbbf50ce9eddc0345319eafc37fa96b;hb=e09b41010ba33a20a87472ee821fa407a5b8da36;hp=1cc61e126e4cc65fd01ee600c76998f92ccfa845;hpb=f93b97fd65072de626c074dbe099a1fff05ce060;p=kvmfornfv.git

diff --git a/kernel/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/kernel/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index 1cc61e126..bfba0b4f1 100644
--- a/kernel/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/kernel/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -1,7 +1,7 @@
 /*
  * P5020/P5010 Silicon/SoC Device Tree Source (pre include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -79,6 +79,14 @@
 		raideng_jr1 = &raideng_jr1;
 		raideng_jr2 = &raideng_jr2;
 		raideng_jr3 = &raideng_jr3;
+
+		fman0 = &fman0;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
+		ethernet3 = &enet3;
+		ethernet4 = &enet4;
+		ethernet5 = &enet5;
 	};
 
 	cpus {