X-Git-Url: https://gerrit.opnfv.org/gerrit/gitweb?a=blobdiff_plain;f=kernel%2Farch%2Farm%2Fboot%2Fdts%2Fsun7i-a20.dtsi;h=e02eb720c4fc1ab192bd76ba0aab0893282ee553;hb=e09b41010ba33a20a87472ee821fa407a5b8da36;hp=2b4847c7cbd415737f4d09d0d2077f380def9326;hpb=f93b97fd65072de626c074dbe099a1fff05ce060;p=kvmfornfv.git diff --git a/kernel/arch/arm/boot/dts/sun7i-a20.dtsi b/kernel/arch/arm/boot/dts/sun7i-a20.dtsi index 2b4847c7c..e02eb720c 100644 --- a/kernel/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/kernel/arch/arm/boot/dts/sun7i-a20.dtsi @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -52,6 +47,7 @@ #include #include +#include #include #include @@ -68,7 +64,8 @@ ranges; framebuffer@0 { - compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; @@ -104,14 +101,14 @@ clocks = <&cpu>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < - /* kHz uV */ - 960000 1400000 - 912000 1400000 - 864000 1300000 - 720000 1200000 - 528000 1100000 - 312000 1000000 - 144000 900000 + /* kHz uV */ + 960000 1400000 + 912000 1400000 + 864000 1300000 + 720000 1200000 + 528000 1100000 + 312000 1000000 + 144000 1000000 >; #cooling-cells = <2>; cooling-min-level = <0>; @@ -203,6 +200,15 @@ clock-output-names = "pll1"; }; + pll2: clk@01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll2-clk"; + reg = <0x01c20008 0x8>; + clocks = <&osc24M>; + clock-output-names = "pll2-1x", "pll2-2x", + "pll2-4x", "pll2-8x"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; @@ -224,7 +230,8 @@ compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; + clock-output-names = "pll6_sata", "pll6_other", "pll6", + "pll6_div_4"; }; pll8: clk@01c20040 { @@ -253,10 +260,16 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; + compatible = "allwinner,sun5i-a13-ahb-clk"; reg = <0x01c20054 0x4>; - clocks = <&axi>; + clocks = <&axi>, <&pll6 3>, <&pll6 1>; clock-output-names = "ahb"; + /* + * Use PLL6 as parent, instead of CPU/AXI + * which has rate changes due to cpufreq + */ + assigned-clocks = <&ahb>; + assigned-clock-parents = <&pll6 3>; }; ahb_gates: clk@01c20060 { @@ -264,6 +277,19 @@ compatible = "allwinner,sun7i-a20-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <3>, <4>, + <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, + <13>, <14>, <16>, + <17>, <18>, <20>, <21>, + <22>, <23>, <25>, + <28>, <32>, <33>, <34>, + <35>, <36>, <37>, <40>, + <41>, <42>, <43>, + <44>, <45>, <46>, + <47>, <49>, <50>, + <52>; clock-output-names = "ahb_usb0", "ahb_ehci0", "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", @@ -292,6 +318,10 @@ compatible = "allwinner,sun7i-a20-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <1>, + <2>, <3>, <4>, + <5>, <6>, <7>, + <8>, <10>; clock-output-names = "apb0_codec", "apb0_spdif", "apb0_ac97", "apb0_iis0", "apb0_iis1", "apb0_pio", "apb0_ir0", "apb0_ir1", @@ -311,6 +341,12 @@ compatible = "allwinner,sun7i-a20-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <3>, <4>, + <5>, <6>, <7>, + <15>, <16>, <17>, + <18>, <19>, <20>, + <21>, <22>, <23>; clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_i2c3", "apb1_can", "apb1_scr", "apb1_ps20", "apb1_ps21", @@ -439,13 +475,22 @@ clock-output-names = "ir1"; }; + keypad_clk: clk@01c200c4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200c4 0x4>; + clocks = <&osc24M>; + clock-output-names = "keypad"; + }; + usb_clk: clk@01c200cc { #clock-cells = <1>; - #reset-cells = <1>; + #reset-cells = <1>; compatible = "allwinner,sun4i-a10-usb-clk"; reg = <0x01c200cc 0x4>; clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + clock-output-names = "usb_ohci0", "usb_ohci1", + "usb_phy"; }; spi3_clk: clk@01c200d4 { @@ -456,6 +501,14 @@ clock-output-names = "spi3"; }; + codec_clk: clk@01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "codec"; + }; + mbus_clk: clk@01c2015c { #clock-cells = <0>; compatible = "allwinner,sun5i-a13-mbus-clk"; @@ -465,10 +518,13 @@ }; /* - * The following two are dummy clocks, placeholders used in the gmac_tx - * clock. The gmac driver will choose one parent depending on the PHY - * interface mode, using clk_set_rate auto-reparenting. - * The actual TX clock rate is not controlled by the gmac_tx clock. + * The following two are dummy clocks, placeholders + * used in the gmac_tx clock. The gmac driver will + * choose one parent depending on the PHY interface + * mode, using clk_set_rate auto-reparenting. + * + * The actual TX clock rate is not controlled by the + * gmac_tx clock. */ mii_phy_tx_clk: clk@2 { #clock-cells = <0>; @@ -527,6 +583,42 @@ #size-cells = <1>; ranges; + sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + }; + + sram_d: sram@00010000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0000 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + nmi_intc: interrupt-controller@01c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; @@ -576,6 +668,7 @@ reg = <0x01c0b000 0x1000>; interrupts = ; clocks = <&ahb_gates 17>; + allwinner,sram = <&emac_sram 1>; status = "disabled"; }; @@ -600,6 +693,8 @@ "sample"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc1: mmc@01c10000 { @@ -615,6 +710,8 @@ "sample"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc2: mmc@01c11000 { @@ -630,6 +727,8 @@ "sample"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc3: mmc@01c12000 { @@ -645,6 +744,21 @@ "sample"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; }; usbphy: phy@01c13400 { @@ -679,6 +793,14 @@ status = "disabled"; }; + crypto: crypto-engine@01c15000 { + compatible = "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ahb_gates 5>, <&ss_clk>; + clock-names = "ahb", "mod"; + }; + spi2: spi@01c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; @@ -742,8 +864,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; pwm0_pins_a: pwm0@0 { @@ -795,6 +916,13 @@ allwinner,pull = ; }; + uart4_pins_b: uart4@1 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "uart4"; + allwinner,drive = ; + allwinner,pull = ; + }; + uart5_pins_a: uart5@0 { allwinner,pins = "PI10", "PI11"; allwinner,function = "uart5"; @@ -896,35 +1024,71 @@ }; spi0_pins_a: spi0@0 { - allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; + allwinner,pins = "PI11", "PI12", "PI13"; + allwinner,function = "spi0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi0_cs0_pins_a: spi0_cs0@0 { + allwinner,pins = "PI10"; + allwinner,function = "spi0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi0_cs1_pins_a: spi0_cs1@0 { + allwinner,pins = "PI14"; allwinner,function = "spi0"; allwinner,drive = ; allwinner,pull = ; }; spi1_pins_a: spi1@0 { - allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,pins = "PI17", "PI18", "PI19"; + allwinner,function = "spi1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi1_cs0_pins_a: spi1_cs0@0 { + allwinner,pins = "PI16"; allwinner,function = "spi1"; allwinner,drive = ; allwinner,pull = ; }; spi2_pins_a: spi2@0 { - allwinner,pins = "PC19", "PC20", "PC21", "PC22"; + allwinner,pins = "PC20", "PC21", "PC22"; allwinner,function = "spi2"; allwinner,drive = ; allwinner,pull = ; }; spi2_pins_b: spi2@1 { - allwinner,pins = "PB14", "PB15", "PB16", "PB17"; + allwinner,pins = "PB15", "PB16", "PB17"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi2_cs0_pins_a: spi2_cs0@0 { + allwinner,pins = "PC19"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi2_cs0_pins_b: spi2_cs0@1 { + allwinner,pins = "PB14"; allwinner,function = "spi2"; allwinner,drive = ; allwinner,pull = ; }; mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; allwinner,function = "mmc0"; allwinner,drive = ; allwinner,pull = ; @@ -938,28 +1102,44 @@ }; mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; + allwinner,pins = "PC6", "PC7", "PC8", + "PC9", "PC10", "PC11"; allwinner,function = "mmc2"; allwinner,drive = ; allwinner,pull = ; }; mmc3_pins_a: mmc3@0 { - allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; + allwinner,pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; allwinner,function = "mmc3"; allwinner,drive = ; allwinner,pull = ; }; - ir0_pins_a: ir0@0 { - allwinner,pins = "PB3","PB4"; + ir0_rx_pins_a: ir0@0 { + allwinner,pins = "PB4"; allwinner,function = "ir0"; allwinner,drive = ; allwinner,pull = ; }; - ir1_pins_a: ir1@0 { - allwinner,pins = "PB22","PB23"; + ir0_tx_pins_a: ir0@1 { + allwinner,pins = "PB3"; + allwinner,function = "ir0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + ir1_rx_pins_a: ir1@0 { + allwinner,pins = "PB23"; + allwinner,function = "ir1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + ir1_tx_pins_a: ir1@1 { + allwinner,pins = "PB22"; allwinner,function = "ir1"; allwinner,drive = ; allwinner,pull = ; @@ -1036,6 +1216,19 @@ status = "disabled"; }; + codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun7i-a20-codec"; + reg = <0x01c22c00 0x40>; + interrupts = ; + clocks = <&apb0_gates 0>, <&codec_clk>; + clock-names = "apb", "codec"; + dmas = <&dma SUN4I_DMA_NORMAL 19>, + <&dma SUN4I_DMA_NORMAL 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; @@ -1129,7 +1322,8 @@ }; i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = ; clocks = <&apb1_gates 0>; @@ -1139,7 +1333,8 @@ }; i2c1: i2c@01c2b000 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; clocks = <&apb1_gates 1>; @@ -1149,7 +1344,8 @@ }; i2c2: i2c@01c2b400 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = ; clocks = <&apb1_gates 2>; @@ -1159,7 +1355,8 @@ }; i2c3: i2c@01c2b800 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = ; clocks = <&apb1_gates 3>; @@ -1169,7 +1366,8 @@ }; i2c4: i2c@01c2c000 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = ; clocks = <&apb1_gates 15>;