Add the rt linux 4.1.3-rt3 as base

[kvmfornfv.git] / kernel / drivers / net / wireless / ath / ath10k / hw.c

diff --git a/kernel/drivers/net/wireless/ath/ath10k/hw.c b/kernel/drivers/net/wireless/ath/ath10k/hw.c
new file mode 100644 (file)
index 0000000..839a879
--- /dev/null
+++ b/kernel/drivers/net/wireless/ath/ath10k/hw.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2014-2015 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/types.h>
+#include "hw.h"
+
+const struct ath10k_hw_regs qca988x_regs = {
+       .rtc_state_cold_reset_mask      = 0x00000400,
+       .rtc_soc_base_address           = 0x00004000,
+       .rtc_wmac_base_address          = 0x00005000,
+       .soc_core_base_address          = 0x00009000,
+       .ce_wrapper_base_address        = 0x00057000,
+       .ce0_base_address               = 0x00057400,
+       .ce1_base_address               = 0x00057800,
+       .ce2_base_address               = 0x00057c00,
+       .ce3_base_address               = 0x00058000,
+       .ce4_base_address               = 0x00058400,
+       .ce5_base_address               = 0x00058800,
+       .ce6_base_address               = 0x00058c00,
+       .ce7_base_address               = 0x00059000,
+       .soc_reset_control_si0_rst_mask = 0x00000001,
+       .soc_reset_control_ce_rst_mask  = 0x00040000,
+       .soc_chip_id_address            = 0x00ec,
+       .scratch_3_address              = 0x0030,
+};
+
+const struct ath10k_hw_regs qca6174_regs = {
+       .rtc_state_cold_reset_mask              = 0x00002000,
+       .rtc_soc_base_address                   = 0x00000800,
+       .rtc_wmac_base_address                  = 0x00001000,
+       .soc_core_base_address                  = 0x0003a000,
+       .ce_wrapper_base_address                = 0x00034000,
+       .ce0_base_address                       = 0x00034400,
+       .ce1_base_address                       = 0x00034800,
+       .ce2_base_address                       = 0x00034c00,
+       .ce3_base_address                       = 0x00035000,
+       .ce4_base_address                       = 0x00035400,
+       .ce5_base_address                       = 0x00035800,
+       .ce6_base_address                       = 0x00035c00,
+       .ce7_base_address                       = 0x00036000,
+       .soc_reset_control_si0_rst_mask         = 0x00000000,
+       .soc_reset_control_ce_rst_mask          = 0x00000001,
+       .soc_chip_id_address                    = 0x000f0,
+       .scratch_3_address                      = 0x0028,
+};