Add the rt linux 4.1.3-rt3 as base
[kvmfornfv.git] / kernel / arch / x86 / kernel / devicetree.c
diff --git a/kernel/arch/x86/kernel/devicetree.c b/kernel/arch/x86/kernel/devicetree.c
new file mode 100644 (file)
index 0000000..6367a78
--- /dev/null
@@ -0,0 +1,310 @@
+/*
+ * Architecture specific OF callbacks.
+ */
+#include <linux/bootmem.h>
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/of_pci.h>
+#include <linux/initrd.h>
+
+#include <asm/hpet.h>
+#include <asm/apic.h>
+#include <asm/pci_x86.h>
+#include <asm/setup.h>
+#include <asm/i8259.h>
+
+__initdata u64 initial_dtb;
+char __initdata cmd_line[COMMAND_LINE_SIZE];
+
+int __initdata of_ioapic;
+
+void __init early_init_dt_scan_chosen_arch(unsigned long node)
+{
+       BUG();
+}
+
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
+{
+       BUG();
+}
+
+void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+{
+       return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
+}
+
+void __init add_dtb(u64 data)
+{
+       initial_dtb = data + offsetof(struct setup_data, data);
+}
+
+/*
+ * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
+ */
+static struct of_device_id __initdata ce4100_ids[] = {
+       { .compatible = "intel,ce4100-cp", },
+       { .compatible = "isa", },
+       { .compatible = "pci", },
+       {},
+};
+
+static int __init add_bus_probe(void)
+{
+       if (!of_have_populated_dt())
+               return 0;
+
+       return of_platform_bus_probe(NULL, ce4100_ids, NULL);
+}
+module_init(add_bus_probe);
+
+#ifdef CONFIG_PCI
+struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
+{
+       struct device_node *np;
+
+       for_each_node_by_type(np, "pci") {
+               const void *prop;
+               unsigned int bus_min;
+
+               prop = of_get_property(np, "bus-range", NULL);
+               if (!prop)
+                       continue;
+               bus_min = be32_to_cpup(prop);
+               if (bus->number == bus_min)
+                       return np;
+       }
+       return NULL;
+}
+
+static int x86_of_pci_irq_enable(struct pci_dev *dev)
+{
+       u32 virq;
+       int ret;
+       u8 pin;
+
+       ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+       if (ret)
+               return ret;
+       if (!pin)
+               return 0;
+
+       virq = of_irq_parse_and_map_pci(dev, 0, 0);
+       if (virq == 0)
+               return -EINVAL;
+       dev->irq = virq;
+       return 0;
+}
+
+static void x86_of_pci_irq_disable(struct pci_dev *dev)
+{
+}
+
+void x86_of_pci_init(void)
+{
+       pcibios_enable_irq = x86_of_pci_irq_enable;
+       pcibios_disable_irq = x86_of_pci_irq_disable;
+}
+#endif
+
+static void __init dtb_setup_hpet(void)
+{
+#ifdef CONFIG_HPET_TIMER
+       struct device_node *dn;
+       struct resource r;
+       int ret;
+
+       dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
+       if (!dn)
+               return;
+       ret = of_address_to_resource(dn, 0, &r);
+       if (ret) {
+               WARN_ON(1);
+               return;
+       }
+       hpet_address = r.start;
+#endif
+}
+
+static void __init dtb_lapic_setup(void)
+{
+#ifdef CONFIG_X86_LOCAL_APIC
+       struct device_node *dn;
+       struct resource r;
+       int ret;
+
+       dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
+       if (!dn)
+               return;
+
+       ret = of_address_to_resource(dn, 0, &r);
+       if (WARN_ON(ret))
+               return;
+
+       /* Did the boot loader setup the local APIC ? */
+       if (!cpu_has_apic) {
+               if (apic_force_enable(r.start))
+                       return;
+       }
+       smp_found_config = 1;
+       pic_mode = 1;
+       register_lapic_address(r.start);
+       generic_processor_info(boot_cpu_physical_apicid,
+                              GET_APIC_VERSION(apic_read(APIC_LVR)));
+#endif
+}
+
+#ifdef CONFIG_X86_IO_APIC
+static unsigned int ioapic_id;
+
+struct of_ioapic_type {
+       u32 out_type;
+       u32 trigger;
+       u32 polarity;
+};
+
+static struct of_ioapic_type of_ioapic_type[] =
+{
+       {
+               .out_type       = IRQ_TYPE_EDGE_RISING,
+               .trigger        = IOAPIC_EDGE,
+               .polarity       = 1,
+       },
+       {
+               .out_type       = IRQ_TYPE_LEVEL_LOW,
+               .trigger        = IOAPIC_LEVEL,
+               .polarity       = 0,
+       },
+       {
+               .out_type       = IRQ_TYPE_LEVEL_HIGH,
+               .trigger        = IOAPIC_LEVEL,
+               .polarity       = 1,
+       },
+       {
+               .out_type       = IRQ_TYPE_EDGE_FALLING,
+               .trigger        = IOAPIC_EDGE,
+               .polarity       = 0,
+       },
+};
+
+static int ioapic_xlate(struct irq_domain *domain,
+                       struct device_node *controller,
+                       const u32 *intspec, u32 intsize,
+                       irq_hw_number_t *out_hwirq, u32 *out_type)
+{
+       struct of_ioapic_type *it;
+       u32 line, idx, gsi;
+
+       if (WARN_ON(intsize < 2))
+               return -EINVAL;
+
+       line = intspec[0];
+
+       if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
+               return -EINVAL;
+
+       it = &of_ioapic_type[intspec[1]];
+
+       idx = (u32)(long)domain->host_data;
+       gsi = mp_pin_to_gsi(idx, line);
+       if (mp_set_gsi_attr(gsi, it->trigger, it->polarity, cpu_to_node(0)))
+               return -EBUSY;
+
+       *out_hwirq = line;
+       *out_type = it->out_type;
+       return 0;
+}
+
+const struct irq_domain_ops ioapic_irq_domain_ops = {
+       .map = mp_irqdomain_map,
+       .unmap = mp_irqdomain_unmap,
+       .xlate = ioapic_xlate,
+};
+
+static void __init dtb_add_ioapic(struct device_node *dn)
+{
+       struct resource r;
+       int ret;
+       struct ioapic_domain_cfg cfg = {
+               .type = IOAPIC_DOMAIN_DYNAMIC,
+               .ops = &ioapic_irq_domain_ops,
+               .dev = dn,
+       };
+
+       ret = of_address_to_resource(dn, 0, &r);
+       if (ret) {
+               printk(KERN_ERR "Can't obtain address from node %s.\n",
+                               dn->full_name);
+               return;
+       }
+       mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
+}
+
+static void __init dtb_ioapic_setup(void)
+{
+       struct device_node *dn;
+
+       for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
+               dtb_add_ioapic(dn);
+
+       if (nr_ioapics) {
+               of_ioapic = 1;
+               return;
+       }
+       printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
+}
+#else
+static void __init dtb_ioapic_setup(void) {}
+#endif
+
+static void __init dtb_apic_setup(void)
+{
+       dtb_lapic_setup();
+       dtb_ioapic_setup();
+}
+
+#ifdef CONFIG_OF_FLATTREE
+static void __init x86_flattree_get_config(void)
+{
+       u32 size, map_len;
+       void *dt;
+
+       if (!initial_dtb)
+               return;
+
+       map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
+
+       initial_boot_params = dt = early_memremap(initial_dtb, map_len);
+       size = of_get_flat_dt_size();
+       if (map_len < size) {
+               early_memunmap(dt, map_len);
+               initial_boot_params = dt = early_memremap(initial_dtb, size);
+               map_len = size;
+       }
+
+       unflatten_and_copy_device_tree();
+       early_memunmap(dt, map_len);
+}
+#else
+static inline void x86_flattree_get_config(void) { }
+#endif
+
+void __init x86_dtb_init(void)
+{
+       x86_flattree_get_config();
+
+       if (!of_have_populated_dt())
+               return;
+
+       dtb_setup_hpet();
+       dtb_apic_setup();
+}