Add the rt linux 4.1.3-rt3 as base

[kvmfornfv.git] / kernel / arch / arm / boot / dts / imx27-phytec-phycard-s-som.dtsi

diff --git a/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
new file mode 100644 (file)
index 0000000..1b62480
--- /dev/null
+++ b/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
+ * and Markus Pargmann, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx27.dtsi"
+
+/ {
+       model = "Phytec pca100";
+       compatible = "phytec,imx27-pca100", "fsl,imx27";
+
+       memory {
+               reg = <0xa0000000 0x08000000>; /* 128MB */
+       };
+};
+
+&cspi1 {
+       fsl,spi-num-chipselects = <2>;
+       cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
+                  <&gpio4 27 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       status = "okay";
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       at24@52 {
+               compatible = "at,24c32";
+               pagesize = <32>;
+               reg = <0x52>;
+       };
+};
+
+&iomuxc {
+       imx27-phycard-s-som {
+               pinctrl_fec1: fec1grp {
+                       fsl,pins = <
+                               MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+                               MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+                               MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+                               MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+                               MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+                               MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+                               MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+                               MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+                               MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+                               MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+                               MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+                               MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+                               MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+                               MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+                               MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+                               MX27_PAD_ATA_DATA13__FEC_COL 0x0
+                               MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+                               MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+                       >;
+               };
+
+               pinctrl_i2c2: i2c2grp {
+                       fsl,pins = <
+                               MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+                               MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+                       >;
+               };
+
+               pinctrl_nfc: nfcgrp {
+                       fsl,pins = <
+                               MX27_PAD_NFRB__NFRB 0x0
+                               MX27_PAD_NFCLE__NFCLE 0x0
+                               MX27_PAD_NFWP_B__NFWP_B 0x0
+                               MX27_PAD_NFCE_B__NFCE_B 0x0
+                               MX27_PAD_NFALE__NFALE 0x0
+                               MX27_PAD_NFRE_B__NFRE_B 0x0
+                               MX27_PAD_NFWE_B__NFWE_B 0x0
+                       >;
+               };
+       };
+};
+
+&nfc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_nfc>;
+       nand-bus-width = <8>;
+       nand-ecc-mode = "hw";
+       nand-on-flash-bbt;
+       status = "okay";
+};