These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / Documentation / devicetree / bindings / power / pd-samsung.txt

diff --git a/kernel/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/kernel/Documentation/devicetree/bindings/power/pd-samsung.txt
similarity index 82%
rename from kernel/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
rename to kernel/Documentation/devicetree/bindings/power/pd-samsung.txt
index 5da38c5..4e94737 100644 (file)
--- a/kernel/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/kernel/Documentation/devicetree/bindings/power/pd-samsung.txt
@@ -19,9 +19,10 @@ Optional Properties:
        domains.
 - clock-names: The following clocks can be specified:
        - oscclk: Oscillator clock.
-       - pclkN, clkN: Pairs of parent of input clock and input clock to the
-               devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
-               are supported currently.
+       - clkN: Input clocks to the devices in this power domain. These clocks
+               will be reparented to oscclk before swithing power domain off.
+               Their original parent will be brought back after turning on
+               the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
        - asbN: Clocks required by asynchronous bridges (ASB) present in
                the power domain. These clock should be enabled during power
                domain on/off operations.
@@ -42,9 +43,8 @@ Example:
        mfc_pd: power-domain@10044060 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10044060 0x20>;
-               clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
-                       <&clock CLK_MOUT_USER_ACLK333>;
-               clock-names = "oscclk", "pclk0", "clk0";
+               clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
+               clock-names = "oscclk", "clk0";
                #power-domain-cells = <0>;
        };