These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / Documentation / devicetree / bindings / pci / hisilicon-pcie.txt

diff --git a/kernel/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/kernel/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
new file mode 100644 (file)
index 0000000..17c6ed9
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+++ b/kernel/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
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+HiSilicon PCIe host bridge DT description
+
+HiSilicon PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible: Should contain "hisilicon,hip05-pcie".
+- reg: Should contain rc_dbi, config registers location and length.
+- reg-names: Must include the following entries:
+  "rc_dbi": controller configuration registers;
+  "config": PCIe configuration space registers.
+- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
+- port-id: Should be 0, 1, 2 or 3.
+
+Optional properties:
+- status: Either "ok" or "disabled".
+- dma-coherent: Present if DMA operations are coherent.
+
+Example:
+       pcie@0xb0080000 {
+               compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
+               reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
+               reg-names = "rc_dbi", "config";
+               bus-range = <0  15>;
+               msi-parent = <&its_pcie>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               device_type = "pci";
+               dma-coherent;
+               ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
+               num-lanes = <8>;
+               port-id = <1>;
+               #interrupts-cells = <1>;
+               interrupts-map-mask = <0xf800 0 0 7>;
+               interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10
+                                 0x0 0 0 2 &mbigen_pcie 2 11
+                                 0x0 0 0 3 &mbigen_pcie 3 12
+                                 0x0 0 0 4 &mbigen_pcie 4 13>;
+               status = "ok";
+       };