These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / Documentation / devicetree / bindings / dma / adi,axi-dmac.txt

diff --git a/kernel/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt b/kernel/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt
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+Analog Device AXI-DMAC DMA controller
+
+Required properties:
+ - compatible: Must be "adi,axi-dmac-1.00.a".
+ - reg: Specification for the controllers memory mapped register map.
+ - interrupts: Specification for the controllers interrupt.
+ - clocks: Phandle and specifier to the controllers AXI interface clock
+ - #dma-cells: Must be 1.
+
+Required sub-nodes:
+ - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
+   the channel sub-nodes the following bindings apply. They must match the
+   configuration options of the peripheral as it was instantiated.
+
+Required properties for adi,channels sub-node:
+ - #size-cells: Must be 0
+ - #address-cells: Must be 1
+
+Required channel sub-node properties:
+ - reg: Which channel this node refers to.
+ - adi,length-width: Width of the DMA transfer length register.
+ - adi,source-bus-width,
+   adi,destination-bus-width: Width of the source or destination bus in bits.
+ - adi,source-bus-type,
+   adi,destination-bus-type: Type of the source or destination bus. Must be one
+   of the following:
+       0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
+       1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
+       2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
+
+Optional channel properties:
+ - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
+   transfers.
+ - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
+
+DMA clients connected to the AXI-DMAC DMA controller must use the format
+described in the dma.txt file using a one-cell specifier. The value of the
+specifier refers to the DMA channel index.
+
+Example:
+
+dma: dma@7c420000 {
+       compatible = "adi,axi-dmac-1.00.a";
+       reg = <0x7c420000 0x10000>;
+       interrupts = <0 57 0>;
+       clocks = <&clkc 16>;
+       #dma-cells = <1>;
+
+       adi,channels {
+               #size-cells = <0>;
+               #address-cells = <1>;
+
+               dma-channel@0 {
+                       reg = <0>;
+                       adi,source-bus-width = <32>;
+                       adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
+                       adi,destination-bus-width = <64>;
+                       adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
+               };
+       };
+};