Add the rt linux 4.1.3-rt3 as base

[kvmfornfv.git] / kernel / Documentation / devicetree / bindings / clock / st / st,clkgen-pll.txt

diff --git a/kernel/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/kernel/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
new file mode 100644 (file)
index 0000000..efb51cf
--- /dev/null
+++ b/kernel/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -0,0 +1,51 @@
+Binding for a ST pll clock driver.
+
+This binding uses the common clock binding[1].
+Base address is located to the parent node. See clock binding[2]
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+
+Required properties:
+
+- compatible : shall be:
+       "st,clkgena-prediv-c65",        "st,clkgena-prediv"
+       "st,clkgena-prediv-c32",        "st,clkgena-prediv"
+
+       "st,clkgena-plls-c65"
+       "st,plls-c32-a1x-0",            "st,clkgen-plls-c32"
+       "st,plls-c32-a1x-1",            "st,clkgen-plls-c32"
+       "st,stih415-plls-c32-a9",       "st,clkgen-plls-c32"
+       "st,stih415-plls-c32-ddr",      "st,clkgen-plls-c32"
+       "st,stih416-plls-c32-a9",       "st,clkgen-plls-c32"
+       "st,stih416-plls-c32-ddr",      "st,clkgen-plls-c32"
+       "st,stih407-plls-c32-a0",       "st,clkgen-plls-c32"
+       "st,stih407-plls-c32-a9",       "st,clkgen-plls-c32"
+       "st,stih407-plls-c32-c0_0",     "st,clkgen-plls-c32"
+       "st,stih407-plls-c32-c0_1",     "st,clkgen-plls-c32"
+
+       "st,stih415-gpu-pll-c32",       "st,clkgengpu-pll-c32"
+       "st,stih416-gpu-pll-c32",       "st,clkgengpu-pll-c32"
+
+- #clock-cells : From common clock binding; shall be set to 1.
+
+- clocks : From common clock binding
+
+- clock-output-names : From common clock binding.
+
+Example:
+
+       clockgen-a@fee62000 {
+               reg = <0xfee62000 0xb48>;
+
+               clk_s_a0_pll: clk-s-a0-pll {
+                       #clock-cells = <1>;
+                       compatible = "st,clkgena-plls-c65";
+
+                       clocks = <&clk_sysin>;
+
+                       clock-output-names = "clk-s-a0-pll0-hs",
+                                            "clk-s-a0-pll0-ls",
+                                            "clk-s-a0-pll1";
+               };
+       };