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These changes are the raw update to qemu-2.6.
[kvmfornfv.git]
/
qemu
/
tcg
/
mips
/
tcg-target.h
diff --git
a/qemu/tcg/mips/tcg-target.h
b/qemu/tcg/mips/tcg-target.h
index
f5ba52c
..
b1cda37
100644
(file)
--- a/
qemu/tcg/mips/tcg-target.h
+++ b/
qemu/tcg/mips/tcg-target.h
@@
-96,6
+96,13
@@
extern bool use_mips32_instructions;
extern bool use_mips32r2_instructions;
#endif
extern bool use_mips32r2_instructions;
#endif
+/* MIPS32R6 instruction set detection */
+#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
+#define use_mips32r6_instructions 1
+#else
+#define use_mips32r6_instructions 0
+#endif
+
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
@@
-105,8
+112,8
@@
extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
-#define TCG_TARGET_HAS_mulu2_i32
1
-#define TCG_TARGET_HAS_muls2_i32
1
+#define TCG_TARGET_HAS_mulu2_i32
(!use_mips32r6_instructions)
+#define TCG_TARGET_HAS_muls2_i32
(!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muluh_i32 1
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_muluh_i32 1
#define TCG_TARGET_HAS_mulsh_i32 1