+static void build_processor_devices(Aml *sb_scope, MachineState *machine,
+ AcpiPmInfo *pm)
+{
+ int i, apic_idx;
+ Aml *dev;
+ Aml *crs;
+ Aml *pkg;
+ Aml *field;
+ Aml *ifctx;
+ Aml *method;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+ CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
+ PCMachineState *pcms = PC_MACHINE(machine);
+
+ /* The current AML generator can cover the APIC ID range [0..255],
+ * inclusive, for VCPU hotplug. */
+ QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
+ g_assert(pcms->apic_id_limit <= ACPI_CPU_HOTPLUG_ID_LIMIT);
+
+ /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
+ dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
+ aml_append(dev,
+ aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
+ );
+ /* device present, functioning, decoding, not shown in UI */
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
+ pm->cpu_hp_io_len)
+ );
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(sb_scope, dev);
+ /* declare CPU hotplug MMIO region and PRS field to access it */
+ aml_append(sb_scope, aml_operation_region(
+ "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len));
+ field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("PRS", 256));
+ aml_append(sb_scope, field);
+
+ /* build Processor object for each processor */
+ for (i = 0; i < apic_ids->len; i++) {
+ int apic_id = apic_ids->cpus[i].arch_id;
+
+ assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
+
+ dev = aml_processor(apic_id, 0, 0, "CP%.02X", apic_id);
+
+ method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
+ aml_append(method,
+ aml_return(aml_call1(CPU_MAT_METHOD, aml_int(apic_id))));
+ aml_append(dev, method);
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method,
+ aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(apic_id))));
+ aml_append(dev, method);
+
+ method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
+ aml_append(method,
+ aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(apic_id),
+ aml_arg(0)))
+ );
+ aml_append(dev, method);
+
+ aml_append(sb_scope, dev);
+ }
+
+ /* build this code:
+ * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
+ */
+ /* Arg0 = Processor ID = APIC ID */
+ method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
+ for (i = 0; i < apic_ids->len; i++) {
+ int apic_id = apic_ids->cpus[i].arch_id;
+
+ ifctx = aml_if(aml_equal(aml_arg(0), aml_int(apic_id)));
+ aml_append(ifctx,
+ aml_notify(aml_name("CP%.02X", apic_id), aml_arg(1))
+ );
+ aml_append(method, ifctx);
+ }
+ aml_append(sb_scope, method);
+
+ /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
+ *
+ * Note: The ability to create variable-sized packages was first
+ * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
+ * ith up to 255 elements. Windows guests up to win2k8 fail when
+ * VarPackageOp is used.
+ */
+ pkg = pcms->apic_id_limit <= 255 ? aml_package(pcms->apic_id_limit) :
+ aml_varpackage(pcms->apic_id_limit);
+
+ for (i = 0, apic_idx = 0; i < apic_ids->len; i++) {
+ int apic_id = apic_ids->cpus[i].arch_id;
+
+ for (; apic_idx < apic_id; apic_idx++) {
+ aml_append(pkg, aml_int(0));
+ }
+ aml_append(pkg, aml_int(apic_ids->cpus[i].cpu ? 1 : 0));
+ apic_idx = apic_id + 1;
+ }
+ aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
+ g_free(apic_ids);
+}
+
+static void build_memory_devices(Aml *sb_scope, int nr_mem,
+ uint16_t io_base, uint16_t io_len)
+{
+ int i;
+ Aml *scope;
+ Aml *crs;
+ Aml *field;
+ Aml *dev;
+ Aml *method;
+ Aml *ifctx;
+
+ /* build memory devices */
+ assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
+ scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
+ aml_append(scope,
+ aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
+ );
+
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
+ );
+ aml_append(scope, aml_name_decl("_CRS", crs));
+
+ aml_append(scope, aml_operation_region(
+ MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
+ aml_int(io_base), io_len)
+ );
+
+ field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
+ AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, /* read only */
+ aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
+ aml_append(field, /* read only */
+ aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
+ aml_append(field, /* read only */
+ aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
+ aml_append(field, /* read only */
+ aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
+ aml_append(field, /* read only */
+ aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
+ aml_append(scope, field);
+
+ field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
+ AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
+ aml_append(field, /* 1 if enabled, read only */
+ aml_named_field(MEMORY_SLOT_ENABLED, 1));
+ aml_append(field,
+ /*(read) 1 if has a insert event. (write) 1 to clear event */
+ aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
+ aml_append(field,
+ /* (read) 1 if has a remove event. (write) 1 to clear event */
+ aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
+ aml_append(field,
+ /* initiates device eject, write only */
+ aml_named_field(MEMORY_SLOT_EJECT, 1));
+ aml_append(scope, field);
+
+ field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
+ AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, /* DIMM selector, write only */
+ aml_named_field(MEMORY_SLOT_SLECTOR, 32));
+ aml_append(field, /* _OST event code, write only */
+ aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
+ aml_append(field, /* _OST status code, write only */
+ aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
+ aml_append(scope, field);
+ aml_append(sb_scope, scope);
+
+ for (i = 0; i < nr_mem; i++) {
+ #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
+ const char *s;
+
+ dev = aml_device("MP%02X", i);
+ aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
+
+ method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+ s = BASEPATH MEMORY_SLOT_CRS_METHOD;
+ aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
+ aml_append(dev, method);
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
+ aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
+ aml_append(dev, method);
+
+ method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
+ s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
+ aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
+ aml_append(dev, method);
+
+ method = aml_method("_OST", 3, AML_NOTSERIALIZED);
+ s = BASEPATH MEMORY_SLOT_OST_METHOD;
+
+ aml_append(method, aml_return(aml_call4(
+ s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
+ )));
+ aml_append(dev, method);
+
+ method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
+ s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
+ aml_append(method, aml_return(aml_call2(
+ s, aml_name("_UID"), aml_arg(0))));
+ aml_append(dev, method);
+
+ aml_append(sb_scope, dev);
+ }
+
+ /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
+ * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
+ */
+ method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
+ for (i = 0; i < nr_mem; i++) {
+ ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
+ aml_append(ifctx,
+ aml_notify(aml_name("MP%.02X", i), aml_arg(1))
+ );
+ aml_append(method, ifctx);
+ }
+ aml_append(sb_scope, method);
+}
+
+static void build_hpet_aml(Aml *table)
+{
+ Aml *crs;
+ Aml *field;
+ Aml *method;
+ Aml *if_ctx;
+ Aml *scope = aml_scope("_SB");
+ Aml *dev = aml_device("HPET");
+ Aml *zero = aml_int(0);
+ Aml *id = aml_local(0);
+ Aml *period = aml_local(1);
+
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
+ aml_append(dev, aml_name_decl("_UID", zero));
+
+ aml_append(dev,
+ aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
+ HPET_LEN));
+ field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("VEND", 32));
+ aml_append(field, aml_named_field("PRD", 32));
+ aml_append(dev, field);
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_store(aml_name("VEND"), id));
+ aml_append(method, aml_store(aml_name("PRD"), period));
+ aml_append(method, aml_shiftright(id, aml_int(16), id));
+ if_ctx = aml_if(aml_lor(aml_equal(id, zero),
+ aml_equal(id, aml_int(0xffff))));
+ {
+ aml_append(if_ctx, aml_return(zero));
+ }
+ aml_append(method, if_ctx);
+
+ if_ctx = aml_if(aml_lor(aml_equal(period, zero),
+ aml_lgreater(period, aml_int(100000000))));
+ {
+ aml_append(if_ctx, aml_return(zero));
+ }
+ aml_append(method, if_ctx);
+
+ aml_append(method, aml_return(aml_int(0x0F)));
+ aml_append(dev, method);
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ aml_append(scope, dev);
+ aml_append(table, scope);
+}
+
+static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
+{
+ Aml *dev, *fdi;
+ uint8_t maxc, maxh, maxs;
+
+ isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
+
+ dev = aml_device("FLP%c", 'A' + idx);
+
+ aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
+
+ fdi = aml_package(16);
+ aml_append(fdi, aml_int(idx)); /* Drive Number */
+ aml_append(fdi,
+ aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
+ /*
+ * the values below are the limits of the drive, and are thus independent
+ * of the inserted media
+ */
+ aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
+ aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
+ aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
+ /*
+ * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
+ * the drive type, so shall we
+ */
+ aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
+ aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
+ aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
+ aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
+ aml_append(fdi, aml_int(0x12)); /* disk_eot */
+ aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
+ aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
+ aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
+ aml_append(fdi, aml_int(0xF6)); /* disk_fill */
+ aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
+ aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
+
+ aml_append(dev, aml_name_decl("_FDI", fdi));
+ return dev;
+}
+
+static Aml *build_fdc_device_aml(ISADevice *fdc)
+{
+ int i;
+ Aml *dev;
+ Aml *crs;
+
+#define ACPI_FDE_MAX_FD 4
+ uint32_t fde_buf[5] = {
+ 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
+ cpu_to_le32(2) /* tape presence (2 == never present) */
+ };
+
+ dev = aml_device("FDC0");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
+ aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
+ aml_append(crs, aml_irq_no_flags(6));
+ aml_append(crs,
+ aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
+ FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
+
+ if (type < FLOPPY_DRIVE_TYPE_NONE) {
+ fde_buf[i] = cpu_to_le32(1); /* drive present */
+ aml_append(dev, build_fdinfo_aml(i, type));
+ }
+ }
+ aml_append(dev, aml_name_decl("_FDE",
+ aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
+
+ return dev;
+}
+
+static Aml *build_rtc_device_aml(void)
+{
+ Aml *dev;
+ Aml *crs;
+
+ dev = aml_device("RTC");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
+ aml_append(crs, aml_irq_no_flags(8));
+ aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ return dev;
+}
+
+static Aml *build_kbd_device_aml(void)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *method;
+
+ dev = aml_device("KBD");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(0x0f)));
+ aml_append(dev, method);
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
+ aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
+ aml_append(crs, aml_irq_no_flags(1));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ return dev;
+}
+
+static Aml *build_mouse_device_aml(void)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *method;
+
+ dev = aml_device("MOU");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(0x0f)));
+ aml_append(dev, method);
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_irq_no_flags(12));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ return dev;
+}
+
+static Aml *build_lpt_device_aml(void)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *method;
+ Aml *if_ctx;
+ Aml *else_ctx;
+ Aml *zero = aml_int(0);
+ Aml *is_present = aml_local(0);
+
+ dev = aml_device("LPT");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_store(aml_name("LPEN"), is_present));
+ if_ctx = aml_if(aml_equal(is_present, zero));
+ {
+ aml_append(if_ctx, aml_return(aml_int(0x00)));
+ }
+ aml_append(method, if_ctx);
+ else_ctx = aml_else();
+ {
+ aml_append(else_ctx, aml_return(aml_int(0x0f)));
+ }
+ aml_append(method, else_ctx);
+ aml_append(dev, method);
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
+ aml_append(crs, aml_irq_no_flags(7));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ return dev;
+}
+
+static Aml *build_com_device_aml(uint8_t uid)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *method;
+ Aml *if_ctx;
+ Aml *else_ctx;
+ Aml *zero = aml_int(0);
+ Aml *is_present = aml_local(0);
+ const char *enabled_field = "CAEN";
+ uint8_t irq = 4;
+ uint16_t io_port = 0x03F8;
+
+ assert(uid == 1 || uid == 2);
+ if (uid == 2) {
+ enabled_field = "CBEN";
+ irq = 3;
+ io_port = 0x02F8;
+ }
+
+ dev = aml_device("COM%d", uid);
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
+ if_ctx = aml_if(aml_equal(is_present, zero));
+ {
+ aml_append(if_ctx, aml_return(aml_int(0x00)));
+ }
+ aml_append(method, if_ctx);
+ else_ctx = aml_else();
+ {
+ aml_append(else_ctx, aml_return(aml_int(0x0f)));
+ }
+ aml_append(method, else_ctx);
+ aml_append(dev, method);
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
+ aml_append(crs, aml_irq_no_flags(irq));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ return dev;
+}
+
+static void build_isa_devices_aml(Aml *table)
+{
+ ISADevice *fdc = pc_find_fdc0();
+
+ Aml *scope = aml_scope("_SB.PCI0.ISA");
+
+ aml_append(scope, build_rtc_device_aml());
+ aml_append(scope, build_kbd_device_aml());
+ aml_append(scope, build_mouse_device_aml());
+ if (fdc) {
+ aml_append(scope, build_fdc_device_aml(fdc));
+ }
+ aml_append(scope, build_lpt_device_aml());
+ aml_append(scope, build_com_device_aml(1));
+ aml_append(scope, build_com_device_aml(2));
+
+ aml_append(table, scope);
+}
+
+static void build_dbg_aml(Aml *table)
+{
+ Aml *field;
+ Aml *method;
+ Aml *while_ctx;
+ Aml *scope = aml_scope("\\");
+ Aml *buf = aml_local(0);
+ Aml *len = aml_local(1);
+ Aml *idx = aml_local(2);
+
+ aml_append(scope,
+ aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
+ field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("DBGB", 8));
+ aml_append(scope, field);
+
+ method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
+
+ aml_append(method, aml_to_hexstring(aml_arg(0), buf));
+ aml_append(method, aml_to_buffer(buf, buf));
+ aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
+ aml_append(method, aml_store(aml_int(0), idx));
+
+ while_ctx = aml_while(aml_lless(idx, len));
+ aml_append(while_ctx,
+ aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
+ aml_append(while_ctx, aml_increment(idx));
+ aml_append(method, while_ctx);
+
+ aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
+ aml_append(scope, method);
+
+ aml_append(table, scope);
+}
+
+static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *method;
+ uint32_t irqs[] = {5, 10, 11};
+
+ dev = aml_device("%s", name);
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_SHARED, irqs, ARRAY_SIZE(irqs)));
+ aml_append(dev, aml_name_decl("_PRS", crs));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_call1("IQST", reg)));
+ aml_append(dev, method);
+
+ method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_or(reg, aml_int(0x80), reg));
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_call1("IQCR", reg)));
+ aml_append(dev, method);
+
+ method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+ aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
+ aml_append(method, aml_store(aml_name("PRRI"), reg));
+ aml_append(dev, method);
+
+ return dev;
+ }
+
+static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *method;
+ uint32_t irqs;
+
+ dev = aml_device("%s", name);
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
+
+ crs = aml_resource_template();
+ irqs = gsi;
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_SHARED, &irqs, 1));
+ aml_append(dev, aml_name_decl("_PRS", crs));
+
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ /*
+ * _DIS can be no-op because the interrupt cannot be disabled.
+ */
+ method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+ aml_append(dev, method);
+
+ method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+ aml_append(dev, method);
+
+ return dev;
+}
+
+/* _CRS method - get current settings */
+static Aml *build_iqcr_method(bool is_piix4)
+{
+ Aml *if_ctx;
+ uint32_t irqs;
+ Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
+ Aml *crs = aml_resource_template();
+
+ irqs = 0;
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+ AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
+ aml_append(method, aml_name_decl("PRR0", crs));
+
+ aml_append(method,
+ aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
+
+ if (is_piix4) {
+ if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
+ aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
+ aml_append(method, if_ctx);
+ } else {
+ aml_append(method,
+ aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
+ aml_name("PRRI")));
+ }
+
+ aml_append(method, aml_return(aml_name("PRR0")));
+ return method;
+}
+
+/* _STA method - get status */
+static Aml *build_irq_status_method(void)
+{
+ Aml *if_ctx;
+ Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
+
+ if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
+ aml_append(if_ctx, aml_return(aml_int(0x09)));
+ aml_append(method, if_ctx);
+ aml_append(method, aml_return(aml_int(0x0B)));
+ return method;
+}
+
+static void build_piix4_pci0_int(Aml *table)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *field;
+ Aml *method;
+ uint32_t irqs;
+ Aml *sb_scope = aml_scope("_SB");
+ Aml *pci0_scope = aml_scope("PCI0");
+
+ aml_append(pci0_scope, build_prt(true));
+ aml_append(sb_scope, pci0_scope);
+
+ field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("PRQ0", 8));
+ aml_append(field, aml_named_field("PRQ1", 8));
+ aml_append(field, aml_named_field("PRQ2", 8));
+ aml_append(field, aml_named_field("PRQ3", 8));
+ aml_append(sb_scope, field);
+
+ aml_append(sb_scope, build_irq_status_method());
+ aml_append(sb_scope, build_iqcr_method(true));
+
+ aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
+ aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
+ aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
+ aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
+
+ dev = aml_device("LNKS");
+ {
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(4)));
+
+ crs = aml_resource_template();
+ irqs = 9;
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+ AML_ACTIVE_HIGH, AML_SHARED,
+ &irqs, 1));
+ aml_append(dev, aml_name_decl("_PRS", crs));
+
+ /* The SCI cannot be disabled and is always attached to GSI 9,
+ * so these are no-ops. We only need this link to override the
+ * polarity to active high and match the content of the MADT.
+ */
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(0x0b)));
+ aml_append(dev, method);
+
+ method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_name("_PRS")));
+ aml_append(dev, method);
+
+ method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+ aml_append(dev, method);
+ }
+ aml_append(sb_scope, dev);
+
+ aml_append(table, sb_scope);
+}
+
+static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
+{
+ int i;
+ int head;
+ Aml *pkg;
+ char base = name[3] < 'E' ? 'A' : 'E';
+ char *s = g_strdup(name);
+ Aml *a_nr = aml_int((nr << 16) | 0xffff);
+
+ assert(strlen(s) == 4);
+
+ head = name[3] - base;
+ for (i = 0; i < 4; i++) {
+ if (head + i > 3) {
+ head = i * -1;
+ }
+ s[3] = base + head + i;
+ pkg = aml_package(4);
+ aml_append(pkg, a_nr);
+ aml_append(pkg, aml_int(i));
+ aml_append(pkg, aml_name("%s", s));
+ aml_append(pkg, aml_int(0));
+ aml_append(ctx, pkg);
+ }
+ g_free(s);
+}
+
+static Aml *build_q35_routing_table(const char *str)
+{
+ int i;
+ Aml *pkg;
+ char *name = g_strdup_printf("%s ", str);
+
+ pkg = aml_package(128);
+ for (i = 0; i < 0x18; i++) {
+ name[3] = 'E' + (i & 0x3);
+ append_q35_prt_entry(pkg, i, name);
+ }
+
+ name[3] = 'E';
+ append_q35_prt_entry(pkg, 0x18, name);
+
+ /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
+ for (i = 0x0019; i < 0x1e; i++) {
+ name[3] = 'A';
+ append_q35_prt_entry(pkg, i, name);
+ }
+
+ /* PCIe->PCI bridge. use PIRQ[E-H] */
+ name[3] = 'E';
+ append_q35_prt_entry(pkg, 0x1e, name);
+ name[3] = 'A';
+ append_q35_prt_entry(pkg, 0x1f, name);
+
+ g_free(name);
+ return pkg;
+}
+
+static void build_q35_pci0_int(Aml *table)
+{
+ Aml *field;
+ Aml *method;
+ Aml *sb_scope = aml_scope("_SB");
+ Aml *pci0_scope = aml_scope("PCI0");
+
+ /* Zero => PIC mode, One => APIC Mode */
+ aml_append(table, aml_name_decl("PICF", aml_int(0)));
+ method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
+ {
+ aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
+ }
+ aml_append(table, method);
+
+ aml_append(pci0_scope,
+ aml_name_decl("PRTP", build_q35_routing_table("LNK")));
+ aml_append(pci0_scope,
+ aml_name_decl("PRTA", build_q35_routing_table("GSI")));
+
+ method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
+ {
+ Aml *if_ctx;
+ Aml *else_ctx;
+
+ /* PCI IRQ routing table, example from ACPI 2.0a specification,
+ section 6.2.8.1 */
+ /* Note: we provide the same info as the PCI routing
+ table of the Bochs BIOS */
+ if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
+ aml_append(if_ctx, aml_return(aml_name("PRTP")));
+ aml_append(method, if_ctx);
+ else_ctx = aml_else();
+ aml_append(else_ctx, aml_return(aml_name("PRTA")));
+ aml_append(method, else_ctx);
+ }
+ aml_append(pci0_scope, method);
+ aml_append(sb_scope, pci0_scope);
+
+ field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("PRQA", 8));
+ aml_append(field, aml_named_field("PRQB", 8));
+ aml_append(field, aml_named_field("PRQC", 8));
+ aml_append(field, aml_named_field("PRQD", 8));
+ aml_append(field, aml_reserved_field(0x20));
+ aml_append(field, aml_named_field("PRQE", 8));
+ aml_append(field, aml_named_field("PRQF", 8));
+ aml_append(field, aml_named_field("PRQG", 8));
+ aml_append(field, aml_named_field("PRQH", 8));
+ aml_append(sb_scope, field);
+
+ aml_append(sb_scope, build_irq_status_method());
+ aml_append(sb_scope, build_iqcr_method(false));
+
+ aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
+ aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
+ aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
+ aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
+ aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
+ aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
+ aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
+ aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
+
+ aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
+ aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
+ aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
+ aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
+ aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
+ aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
+ aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
+ aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
+
+ aml_append(table, sb_scope);
+}
+
+static void build_q35_isa_bridge(Aml *table)
+{
+ Aml *dev;
+ Aml *scope;
+ Aml *field;
+
+ scope = aml_scope("_SB.PCI0");
+ dev = aml_device("ISA");
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
+
+ /* ICH9 PCI to ISA irq remapping */
+ aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
+ aml_int(0x60), 0x0C));
+
+ aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
+ aml_int(0x80), 0x02));
+ field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("COMA", 3));
+ aml_append(field, aml_reserved_field(1));
+ aml_append(field, aml_named_field("COMB", 3));
+ aml_append(field, aml_reserved_field(1));
+ aml_append(field, aml_named_field("LPTD", 2));
+ aml_append(dev, field);
+
+ aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
+ aml_int(0x82), 0x02));
+ /* enable bits */
+ field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
+ aml_append(field, aml_named_field("CAEN", 1));
+ aml_append(field, aml_named_field("CBEN", 1));
+ aml_append(field, aml_named_field("LPEN", 1));
+ aml_append(dev, field);
+
+ aml_append(scope, dev);
+ aml_append(table, scope);
+}
+
+static void build_piix4_pm(Aml *table)
+{
+ Aml *dev;
+ Aml *scope;
+
+ scope = aml_scope("_SB.PCI0");
+ dev = aml_device("PX13");
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
+
+ aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
+ aml_int(0x00), 0xff));
+ aml_append(scope, dev);
+ aml_append(table, scope);
+}
+
+static void build_piix4_isa_bridge(Aml *table)
+{
+ Aml *dev;
+ Aml *scope;
+ Aml *field;
+
+ scope = aml_scope("_SB.PCI0");
+ dev = aml_device("ISA");
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
+
+ /* PIIX PCI to ISA irq remapping */
+ aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
+ aml_int(0x60), 0x04));
+ /* enable bits */
+ field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
+ /* Offset(0x5f),, 7, */
+ aml_append(field, aml_reserved_field(0x2f8));
+ aml_append(field, aml_reserved_field(7));
+ aml_append(field, aml_named_field("LPEN", 1));
+ /* Offset(0x67),, 3, */
+ aml_append(field, aml_reserved_field(0x38));
+ aml_append(field, aml_reserved_field(3));
+ aml_append(field, aml_named_field("CAEN", 1));
+ aml_append(field, aml_reserved_field(3));
+ aml_append(field, aml_named_field("CBEN", 1));
+ aml_append(dev, field);
+
+ aml_append(scope, dev);
+ aml_append(table, scope);
+}
+
+static void build_piix4_pci_hotplug(Aml *table)
+{
+ Aml *scope;
+ Aml *field;
+ Aml *method;
+
+ scope = aml_scope("_SB.PCI0");
+
+ aml_append(scope,
+ aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
+ field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("PCIU", 32));
+ aml_append(field, aml_named_field("PCID", 32));
+ aml_append(scope, field);
+
+ aml_append(scope,
+ aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
+ field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("B0EJ", 32));
+ aml_append(scope, field);
+
+ aml_append(scope,
+ aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
+ field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("BNUM", 32));
+ aml_append(scope, field);
+
+ aml_append(scope, aml_mutex("BLCK", 0));
+
+ method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
+ aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
+ aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
+ aml_append(method,
+ aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
+ aml_append(method, aml_release(aml_name("BLCK")));
+ aml_append(method, aml_return(aml_int(0)));
+ aml_append(scope, method);
+
+ aml_append(table, scope);
+}
+
+static Aml *build_q35_osc_method(void)
+{
+ Aml *if_ctx;
+ Aml *if_ctx2;
+ Aml *else_ctx;
+ Aml *method;
+ Aml *a_cwd1 = aml_name("CDW1");
+ Aml *a_ctrl = aml_name("CTRL");
+
+ method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
+ aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
+
+ if_ctx = aml_if(aml_equal(
+ aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
+ aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+ aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+
+ aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
+ aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
+
+ /*
+ * Always allow native PME, AER (no dependencies)
+ * Never allow SHPC (no SHPC controller in this system)
+ */
+ aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
+
+ if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
+ /* Unknown revision */
+ aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
+ aml_append(if_ctx, if_ctx2);
+
+ if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
+ /* Capabilities bits were masked */
+ aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
+ aml_append(if_ctx, if_ctx2);
+
+ /* Update DWORD3 in the buffer */
+ aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
+ aml_append(method, if_ctx);
+
+ else_ctx = aml_else();
+ /* Unrecognized UUID */
+ aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
+ aml_append(method, else_ctx);
+
+ aml_append(method, aml_return(aml_arg(3)));
+ return method;
+}
+