-/* Input Color Space (IO register 0x02, [7:4]) */
-enum adv7842_inp_color_space {
- ADV7842_INP_COLOR_SPACE_LIM_RGB = 0,
- ADV7842_INP_COLOR_SPACE_FULL_RGB = 1,
- ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
- ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
- ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4,
- ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5,
- ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
- ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
- ADV7842_INP_COLOR_SPACE_AUTO = 0xf,
-};
-
-/* Select output format (IO register 0x03, [7:0]) */
-enum adv7842_op_format_sel {
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a,
- ADV7842_OP_FORMAT_SEL_DDR_422_8 = 0x20,
- ADV7842_OP_FORMAT_SEL_DDR_422_10 = 0x21,
- ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22,
- ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23,
- ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24,
- ADV7842_OP_FORMAT_SEL_SDR_444_24 = 0x40,
- ADV7842_OP_FORMAT_SEL_SDR_444_30 = 0x41,
- ADV7842_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42,
- ADV7842_OP_FORMAT_SEL_DDR_444_24 = 0x60,
- ADV7842_OP_FORMAT_SEL_DDR_444_30 = 0x61,
- ADV7842_OP_FORMAT_SEL_DDR_444_36 = 0x62,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86,
- ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a,
-};
-