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These changes are the raw update to linux-4.4.6-rt14. Kernel sources
[kvmfornfv.git]
/
kernel
/
drivers
/
gpu
/
drm
/
radeon
/
radeon_irq.c
diff --git
a/kernel/drivers/gpu/drm/radeon/radeon_irq.c
b/kernel/drivers/gpu/drm/radeon/radeon_irq.c
index
244b19b
..
688afb6
100644
(file)
--- a/
kernel/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/
kernel/drivers/gpu/drm/radeon/radeon_irq.c
@@
-62,12
+62,12
@@
static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
}
RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
}
-int radeon_enable_vblank(struct drm_device *dev,
int crtc
)
+int radeon_enable_vblank(struct drm_device *dev,
unsigned int pipe
)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
{
drm_radeon_private_t *dev_priv = dev->dev_private;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
- switch (
crtc
) {
+ switch (
pipe
) {
case 0:
r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
break;
case 0:
r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
break;
@@
-75,12
+75,12
@@
int radeon_enable_vblank(struct drm_device *dev, int crtc)
r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
break;
default:
r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
break;
default:
- DRM_ERROR("tried to enable vblank on non-existent crtc %
d
\n",
-
crtc
);
+ DRM_ERROR("tried to enable vblank on non-existent crtc %
u
\n",
+
pipe
);
return -EINVAL;
}
} else {
return -EINVAL;
}
} else {
- switch (
crtc
) {
+ switch (
pipe
) {
case 0:
radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
break;
case 0:
radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
break;
@@
-88,8
+88,8
@@
int radeon_enable_vblank(struct drm_device *dev, int crtc)
radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
break;
default:
radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
break;
default:
- DRM_ERROR("tried to enable vblank on non-existent crtc %
d
\n",
-
crtc
);
+ DRM_ERROR("tried to enable vblank on non-existent crtc %
u
\n",
+
pipe
);
return -EINVAL;
}
}
return -EINVAL;
}
}
@@
-97,12
+97,12
@@
int radeon_enable_vblank(struct drm_device *dev, int crtc)
return 0;
}
return 0;
}
-void radeon_disable_vblank(struct drm_device *dev,
int crtc
)
+void radeon_disable_vblank(struct drm_device *dev,
unsigned int pipe
)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
{
drm_radeon_private_t *dev_priv = dev->dev_private;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
- switch (
crtc
) {
+ switch (
pipe
) {
case 0:
r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
break;
case 0:
r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
break;
@@
-110,12
+110,12
@@
void radeon_disable_vblank(struct drm_device *dev, int crtc)
r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
break;
default:
r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
break;
default:
- DRM_ERROR("tried to enable vblank on non-existent crtc %
d
\n",
-
crtc
);
+ DRM_ERROR("tried to enable vblank on non-existent crtc %
u
\n",
+
pipe
);
break;
}
} else {
break;
}
} else {
- switch (
crtc
) {
+ switch (
pipe
) {
case 0:
radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
break;
case 0:
radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
break;
@@
-123,8
+123,8
@@
void radeon_disable_vblank(struct drm_device *dev, int crtc)
radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
break;
default:
radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
break;
default:
- DRM_ERROR("tried to enable vblank on non-existent crtc %
d
\n",
-
crtc
);
+ DRM_ERROR("tried to enable vblank on non-existent crtc %
u
\n",
+
pipe
);
break;
}
}
break;
}
}
@@
-255,7
+255,7
@@
static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
return ret;
}
return ret;
}
-u32 radeon_get_vblank_counter(struct drm_device *dev,
int crtc
)
+u32 radeon_get_vblank_counter(struct drm_device *dev,
unsigned int pipe
)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@
-264,18
+264,18
@@
u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
return -EINVAL;
}
return -EINVAL;
}
- if (
crtc < 0 || crtc
> 1) {
- DRM_ERROR("Invalid crtc %
d\n", crtc
);
+ if (
pipe
> 1) {
+ DRM_ERROR("Invalid crtc %
u\n", pipe
);
return -EINVAL;
}
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
return -EINVAL;
}
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
- if (
crtc
== 0)
+ if (
pipe
== 0)
return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
else
return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
} else {
return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
else
return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
} else {
- if (
crtc
== 0)
+ if (
pipe
== 0)
return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
else
return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
else
return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);